超深亞微米 的英文怎麼說
中文拼音 [chāoshēnyǎwéimǐ]
超深亞微米
英文
ultra-deesubmicron-
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。Experimental results in this paper show our approaches can be efficiently used in delay testing for complex circuits with noise effects
實驗表明，本文的方法可以應用在復雜超深亞微米電路的延時故障測試中，有一定推廣價值。Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple - period sensitization is presented. a novel noise estimation method based on boolean process is first presented in this paper, using transition numbers to describe noise effects. then combined with the selection method of long sensitization paths based on waveform sensitization, a test generation approach that could generate the noisiest sensitization waveforms for long sensitizatizable paths is presented
為了適應超深亞微米電路測試的要求，本文建立了一種新的基於布爾過哈爾濱工程大學博士學位論文程論的邏輯級噪聲預測模型，用波形多項式描述的同時發生的跳變數來預測l卜足聲大小，並生成能產生最大跳變數目的輸入波形;然後同基於波形敏化的長敏化通路選擇法相結合，形成一種能產生最大噪聲效應的敏化測試波形生成新方法。Longer paths tend to be sensitive to crosstalk - induced delay effects because of their short slack time
因此，超深亞微米工藝下，在設計驗證、測試階段需要對串擾問題給予認真對待。Especially with the use and advancement of vdsm ( very - deep - sub - micron ) technology, the faults during manufacturing become more multiple and difficult to test
尤其是超深亞微米（ vdsm ）工藝的使用，生產過程中出現的故障也越來越多樣、難測。With the rapid developments of slsi technology, the system on a chip ( soc ) technology supported by very deep sub - micron ( vdsm ) and ip - reuse has become the developmental trend of international slsi and the ic mainstream in the 21st century
隨著超大規模集成電路工藝技術的發展，以超深亞微米工藝和ip核復用技術為支撐的系統晶元技術（ soc ）是國際超大規模集成電路發展的趨勢和二十一世紀集成電路技術的主流。The rectilinear steiner minimal tree rsmt problem is one of the fundamental problems in physical design, especially in routing, which is known to be np - complete. this paper presents an algorithm, called aco - steiner, for rsmt construction based on ant colony optimization
製造工藝由超深亞微米vdsm進入到納米nanometer階段，作為物理設計physical design重要階段之一的布線routing ，其演算法研究與工具設計面臨新的挑戰。With the deep sub - micron process being mainstream technique in semiconductor production, the shrinking scale and the expanding size & complexity bring about a series of severe problems, which poses a great challenge on asic ( application specific integrated circuits ) design. we must consider synthesis and test requirements in the early time of front - end design
隨著超深亞微米工藝成為半導體業界的主流加工工藝，日漸細微的器件尺寸以及不斷膨脹的設計規模和復雜度引起了一系列嚴峻的問題，給asic設計帶來了巨大的挑戰，迫切要求在前端設計時就開始考慮綜合、驗證和測試的需要。When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。This dissertation investigates the breakdown theory and reliability characterization methods of the time dependent dielectric breakdown ( tddb ) for the ultra - thin gate oxide, and the hot - carrier effect ( hce ) in deep sub - micron mosfet ' s
本文對超薄柵氧化層經時擊穿（ tddb ）擊穿機理和可靠性表徵方法以及深亞微米mos器件熱載流子效應（ hce ）進行了系統研究。This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design
本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。With the coming of vlsfs sub - micron era, low - power technique has been a growing demand in vlsi design
隨著集成電路進入深亞微米時代，功耗問題已成為超大規模集成電路設計考慮的重要因素。Based on the project ? esearch on the theory of sub - deep micro and super high speed multimedia chip design ? ( no. 69876010 ) sponsored by the national natural science foundation, the project ? esearch on mixing technology of high speed multimedia data ? ( no. 98035901 ) sponsored by the doctoral research foundation of the state ministry of education and the project ? esearch on the high level description of eight - bit microprocessor ? ( no. 97 - 758 - 01 - 53. 7 ) sponsored by the state ? ? inth five - year program ? a deep research on interface ip, multimedia ip and microprocessor ip is made in this dissertation
本文基於國家自然科學基金資助項目「深亞微米超高速多媒體晶元設計理論的研究」 （項目編號： 69876010 ） 、國家教委博士點基金資助項目「高速多媒體數據混合技術的研究」 （項目編號： 98035901 ）和國家「九五」重點科技攻關項目「 8位微處理器高層語言描述的研究」 （項目編號： 97 - 758 - 01 - 53 - 07 ） ，重點對相位抖動理論、介面類ip核、多媒體類ip核、微處理器類ip核設計進行了深入的研究。分享友人