輸出寄存器號 的英文怎麼說
中文拼音 [shūchūjìcúnqìháo]
輸出寄存器號
英文
output register number- 輸 : Ⅰ動詞1 (運輸; 運送) transport; convey 2 [書面語] (捐獻) contribute money; donate 3 (失敗) l...
- 存 : 動詞1 (存在; 生存) exist; live; survive 2 (儲存; 保存) store; keep 3 (蓄積; 聚集) accumulat...
- 器 : 名詞1. (器具) implement; utensil; ware 2. (器官) organ 3. (度量; 才能) capacity; talent 4. (姓氏) a surname
- 號 : 號Ⅰ名1 (名稱) name 2 (別號; 字) assumed name; alternative name3 (商店) business house 4 (...
- 輸出 : 1 (從內部送到外部) export 2 [電學] output; outcome; outlet; out fan; fanout; 輸出變壓器 output ...
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Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals
搭建了一個驗證系統,通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態,用邏輯分析儀採集輸出的信號。In this paper, we discuss a kind of filter generator whose filter functions have less input bits than the degree of the linear feedback shift register ( lfsr ). by analyzing the structure of the filter generator and its equivalent system, we give out a conditional search algorithm ( csa ) to attack this kind of filter generators
針對濾波函數f ( x )的輸入比特數m少於線性反饋移位寄存器級數n的濾波生成器,本文通過分析其等價的組合生成器的結構,以及不同節拍上驅動序列的各個符號之間的制約關系,給出了廣義解序列的概念,並提出了類似遍歷二叉樹的條件搜索演算法csa ,用於攻擊該類特殊的濾波序列。Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method
該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號,用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率,而且這一調頻過程幾乎是連續的(實際上是眾多離散點構成的線性近似) 。The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals
使用xillinx的fpgaxc2550pq208 ,經過fpga的實現流程,把配置文件配置到xczs5opqzos ,搭建了一個驗證系統,通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態,用邏輯分析儀採集輸出的信號。The a / d and cap circuits on dsp sample the voltage and current signals coming from the signal sampling circuit and the speed signal of the motor respectively. the " dead time " register of the dsp prevent directive - through of the igbts on the up and the down bridge arms
利用dsp上的死區寄存器設置ipm驅動信號的死區時間防止上下橋臂igbt的直通;利用板上集成的a / d轉換器採集經過板級外圍電路處理的電路信號;利用板上的捕獲單元cap採集通過轉速計的輸出從而得到電機的轉速。分享友人