進位寄存器 的英文怎麼說
中文拼音 [jìnwèijìcúnqì]
進位寄存器
英文
carry register-
This register contains carry and overflow information from integer arithmetic operations
這個寄存器存放整數運算操作的進位以及溢出信息。The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation
再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。With these data structures, code modules, and system registers initialized, the processor can be switched to protected mode by loading control register cr0 with a value that sets the pe flag ( bit 0 )
當設置好這些數據結構，代碼段以及系統寄存器之後，可以通過設置控制寄存器cr0的pe位（第0位）為1來進入保護模式。Computer architecture, barcelona, spain, june 27 - july 1, 1998, pp. 282 - 292. 6 buyuktosunoglu a et al. a circuit level implementation of an adaptive issue queue for power - aware microprocessors
2對位於第二級的發射隊列利用寄存器標簽進行多體劃分，更進一步減小發射隊列的大小和比較器的位寬。Not only fault model, but also test arithmetic demand to be farther improved. the thesis, focusing on the 20 - port register file, makes a fault analysis, particularly in complex bridge fault and crosstalk coupling fault aroused by word - line and bit - line of 20 - port
本文針對所設計的寄存器文件進行了故障分析，特別對20埠字線、位線引起的復雜橋接故障和串擾導致的耦合故障進行了詳盡論述。Controlling system is composed of drive circuit, locking memory, shift register. temperature compensating circuit and drive power circuit are also needed
控制系統是由驅動電路、鎖存器、移位寄存器等組成，此外還需要溫度補償電路和驅動電源電路，本文對控制系統進行了詳細的論述。Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz
本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。Chapter five discusses the design and the process of the generation of the control function, including counter, accumulator, comparator, shift register, demultiplexer, collector, access record. chapter six gives some advice and opinions on how to improve this computer software
其次介紹了計數器、累加器、比較器、多路輸出選擇、移位寄存器控制項；數據類中的收集器、訪問記錄/部分輸出記錄等控制項的功能介紹和編程思路以及使用實例第六章對平臺的完善和改進闡述了一些個人的建議和想法。Fields would be made directly to main memory, instead of to registers or the local processor cache, and that actions on volatile variables on behalf of a thread are performed in the order that the thread requested
欄位的讀寫直接在主存而不是寄存器或者本地處理器緩存中進行，並且代表線程對volatile變量進行的這些操作是按線程要求的順序進行的。In the part of voice encryption, spatiotemporal chaotic system ( ocoml model ) and lfsr are used to generate multidimensional pseudo - random sequence. this sequence has a longer period, better randomicity, passing the verification of fips 140 - 2 security requirements. using the key stream generated by it to encrypt the voice gets a better security
在語音加密方面，本文利用時空混沌系統（單向耦合映象格子模型）與線性移位寄存器產生了高維的偽隨機序列，該序列周期很長，具有更強的隨機性，通過了fips140 - 2的安全性能驗證，利用其作為密鑰流對語音信號進行加密，獲得了更高的保密性。The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral
它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。After deeply studying all kinds of problems of current actualization methods, we put forward to a new actualization method of the technology of physical isolation on the base of cpld. we make a lot of research on data encryption and describe the design method of the encryption chip on the base of lfsr ( linear feedback shift register ). after putting forward to the whole design procedure, we design an encryption chip on the base of lfsr, which can provide the high - quantity data stream of encrtption
在深入研究了常見物理隔離技術實現方案中存在的各種問題后，提出了一種基於cpld的全新實現方案；同時，對于存儲信息的加密也進行了研究，詳細闡述了基於移位寄存器的非線性組合序列密碼的設計方法，提出了完整的設計流程，並設計了一個基於fpga的非線性組合反饋序列密碼晶元，該晶元能提供高質量的偽隨機密鑰流。Fcsr sequences are the abbreviation for feedback with carry shift register sequences. among these, the most important are maximum - period fcsr sequences, that is, l - sequences
帶進位反饋移位寄存器序列簡稱fcsr序列，其中最重要的是極大周期fcsr序列，即l -序列To implement dynamic binary translation effectively, several optimized methods come up in this thesis : efla algorithm to enhance the efficiency of emulating the condition code of the source platform on target platform ; two algorithms to handle the active and passive exception in application level ; and a translation - guided algorithm for register allocation
針對動態二進制翻譯，本文提出了若干種優化方案:提高在目標機器上模擬源機器標志位效率的efla演算法;處理應用級主動異常和被動異常的兩個演算法;翻譯制導的寄存器優化演算法。A switch ic for analog signal processing is designed and implemented, which can fulfill the functions of sampling, weighting, controlling and summing of high frequency analog signals. the circuit consists of three parts : four channel analog switches, a voltage reference and the control circuitry. each analog switch is comprised of two high - transconductance n - mosfets with high w / l ratio, which realize the fine tuning and coarse tuning of the input signal respectively
本文研究並設計了一種可對高頻信號進行取樣、加權、控制、疊加的模擬信號處理丌關集成電路，它包括模擬開關、電壓基準源和移位寄存器三個功能模塊，通過兩個高寬長比的高跨導nmos晶體管實現權值的粗調和微調。Generally, each bit or set of bits within the register controls some behavior of the larger device
一般地，在寄存器控制每一二進制位或二進制位的集控制大量設備的一些行為。分享友人