運算單元 的英文怎麼說
中文拼音 [yùnsuàndānyuán]
運算單元
英文
airthmetic unit-
This algorithm is based on the 16 - fft about square root decomposition, and using the phase revolution unit replaces multiplication, and uses the serial butterfly operation unit. at last, gives the correspond realization measure in fpga
本文根據一種基於平方根分解的16點fft演算法，採用相位旋轉因子取代乘法器，並利用串列流水蝴蝶運算單元給出了一種新的實現演算法，並介紹了其在fpga中相應的實現方法。This includes deriving equations of motion automatically and designing a fast operation unit used to compute these equations
其中包括，採用計算機自動推導動力學方程和設計一個用於快速計算動力學方程的運算單元。Fpu float point unit
浮點運算單元After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper
此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。Arithmetic logic unit
算術邏輯運算單元In hardware circuit, epf10k30e is chosen as core unit of control and operation
在硬體電路中，使用altera公司的epf10k30e作為核心控制及運算單元。The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaining an operation result
運算單元則針對有效動態?圍的位元數進行既定運算，藉以得到一運算結果。16 mai k et al. smart memories : a modular reconfigurable architecture. in 2000 isca, vancouver, canada, pp. 161 - 171
比較imagine ，在硬體上我們適當增加了核心控制和運算單元的靈活性，軟體可管理的存儲單元。When the system is implemented by fpga, the software can be downloaded from our host pc, and the data can be saved in fpga
在fpga實現的環境中，系統軟體可以從pc機下載，存儲mp3數據流文件，由整數運算單元完成解碼工作后通過codec播放。According the distance away from cpu core near to far, the acces speed of memory falls down from faster to lower, but the cost from higher to less
這種多級存儲層次的速度則根據距離cpu核心運算單元的近遠，呈現出逐級按級數遞減，成本逐級遞增的特性。An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word - length restoration unit
一種低功率消耗的算術裝置，其利用輸入主級閂、動態?圍偵測單元、控制轉換仆級閂、運算單元、位元數還原單元以構成。For fast computation of dynamic equations, a special operation unit is referred according to the computing structure of dynamic equations. the pipeline idea is used in this operation unit. there are a adder, a multiplier and a trigonometric function generator in it
在動力學方程的快速計算方面，根據動力學方程的計算結構提出一種可用於專門計算機器人動力學方程的運算單元，此運算單元採用流水線結構，其運算部分包括加法器、乘法器和一個三角函數發生器。Any j2ee application that runs within the cell can potentially access any j2ee resource
任何在計算單元內運行的j2ee應用程序都可以潛在地訪問任何j2ee資源。The material ways are to model the honeycomb wall as an impredence surface, to express the infinite honeycomb by using periodic green ' s function, and using method of moment to establish the mathematic model, in applying the methods of moments, we choose the roof function as basic function and choose the razor function as test function ; by equating the incident field to sum of the scattering field and impledance field ; we will set up the integral equation for the surface current, solving it by mom equation. then gain it ' s reflected coefficient ' s numerical result. and we propose first the definition of the equivalent electromagnetic parameters and present a method to calculate them from the gained reflection coefficient
具體方法就是將浸漬吸收劑的蜂窩壁用表面阻抗表示，將無限大的周期結構的電場用周期格林函數來表示，選取有耗蜂窩結構中具有代表性的基本計算單元應用矩量法建立數學模型，在運用矩量法時用屋頂函數作為基函數，刀片函數作為檢驗函數，根據蜂窩壁表面電場必須滿足入射電場等於散射電場和阻抗電場之和的規律，推導表面電場積分方程，求解蜂窩結構的表面電流，利用蜂窩的周期規律得到無限大均勻周期陣列的散射電場。Floating - point unit is a special microprocessor circuitry unit that deals with floating - point arithmetic operations, which is widely used in scientific arithmetic, cpu, dsp ( digital signal processing ) and image processing, the thesis discusses how to implement high - performance floating - point processing unit based on the research of its implementation algorithm and its implementation structure
浮點運算單元（ fpu ）是處理器中專門進行浮點算術運算的電路單元，廣泛應用在科學計算、 cpu 、 dsp和圖象處理。論文從浮點運算單元的實現演算法和結構的研究出發，討論如何實現高性能浮點運算單元。Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition
Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員，其上包括：具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器，主頻160mhz ， sram存儲器， flash存儲器具有三路uart介面，一路ps 2介面， led發光二極體控制電路，中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。Simply run each cell with a different operating system user id, different encryption keys, and different administrative passwords
直接使用不同的操作系統用戶id 、不同的加密密鑰和不同的管理密碼運行每個計算單元即可。In modern vlsi technology, hundreds of thousands of arithmetic units fit on a 1cm 2 chip. the challenge is supplying them with instructions and data. stream architecture is able to solve the problem well
在摩爾定律作用下，在單晶元上可集成的晶體管數快速增長，單晶元擁有成百上千的運算單元不再是問題，關鍵是如何給如此多的alu提供足夠的指令和數據。Thirdly dct is implemented using chen fast dct algorithm. we transform float - point arithmetic into fixed - point arithmetic, which meeting the precision requirements of the ieee 1180 standard, to accord with fixed - point c6201 dsps
隨后在dct變換編碼中，採用chen快速dct演算法，在保證idct精度符合ieee1180標準條件下，將浮點dct系數轉化為與c6201定點dsps運算單元相適應的定點系數。In the multi - module mode both trig signal and reference clock are used for synchronization. the functional module supports dma with the dsp, which frees the dsp ' s core processor and entitles the real - time digital signal processing
在數據傳輸方面無論是通過外部總線介面還是數據鏈路介面，功能模塊與dsp之間都支持dma方式，解放了母板處理器的核心運算單元，使實時信號處理成為可能。分享友人