邊界掃描結構 的英文怎麼說

中文拼音 [biānjièsǎomiáojiēgòu]
邊界掃描結構 英文
boundary-scan architecture
  • 邊 : 邊Ⅰ名詞1 （幾何圖形上夾成角的直線或圍成多邊形的線段） side; section 2 （邊緣） edge; margin; oute...
  • 界 : 名詞1 （相交的地方; 劃分的界限） boundary 2 （一定的范圍） scope; extent 3 （按職業、工作或性別等...
  • 掃 : 掃構詞成分。
  • 描 : 動詞1. （照底樣畫） copy; depict; trace 2. （在原來顏色淡或需改正之處重復塗抹） retouch; touch up
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 邊界 : boundary; frontier; border; borderline; edge range line; periphery
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. Standard test access port and boundary scan architecture

    標準測試存取口及邊界掃描體系結構
  2. International standard ieee 1149. 1 describes the basic circuit structure and performance of boundary scan

    國際標準ieee1149 . 1規定了邊界掃描的基本電路結構和功能。
  3. Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ), boundary scan and internal scan

    Jx5微處理器的測試結構由bist 、邊界掃描和內部掃描三部分組成。
  4. In this paper, we combine the standard modules realize the boundary scan of estarl and also expand it to the test of internal circuit. this structure can save the i / o port of the chip and simplify the testing program

    本文結合標準模塊設計實現了estar1的邊界掃描結構，並進行了擴展，應用到晶元內部測試，節約了測試i / o口消耗，簡化了測試過程。
  5. In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result, the fault coverage is more than 96 %

    本文針對嵌入式微處理器estar1的結構特點，研究並實現了邊界掃描、內部全掃描和內建自測試三種可測性設計技術，取得了良好的效果，故障覆蓋率達到96以上。
  6. As one of the design for testability technology, boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics. thus, the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response

    作為一種結構插入的可測性技術，邊界掃描測試（ bst ）技術將邊界掃描寄存器單元安插在集成電路內部的每個引腳上，其作用相當于設置了施加激勵和觀測響應的內建虛擬探頭。
  7. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  8. Test access port and boundary - scan architecture

    測試存取口及邊界掃描結構
  9. On the other hand, boundary - scan technique intelligent fault diagnostic method was applied to practice. for most digital system, devices with boundary - scan architecture are broadly used. only using four line or five line to connect pc parallel port with cut tap ( test access port ), all the ptvs can be loaded to cut and all homologous prvs can be taken back to intelligent fault diagnosis system

    至於本文採用邊界掃描測試故障診斷技術，是考慮到本系統的通用性和簡潔性，因為對于大多數數字系統而言，具有邊界掃描結構的器件己廣泛應用，本文只需4條或5條信號線就能將pc機和被測邊界掃描電路連接起來，由此極大地簡化了智能故障診斷系統中為實現ptvs加載和prvs獲取而專門設計的介面板電路。
  10. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  11. There are a lot of methods available to create test vector. the thesis addresses their characteristics of the methods and special structure of boundary scan circuit respectively and come to a conclusion of pseudo - exchausive testing the most rational method applied to this situation

    測試矢量的生成方法很多，本文在研究了各種方法的特性，以及邊界掃描電路的特殊結構后，採用了偽窮舉法生成測試矢量。
  12. In this paper, ieee1149. 4 std mixed - signal test bus and its characteristic are studied. according to the structure defined in this standard, test methods of mixed - signal circuits are studied. the mixed - signal boundary - scan test system, which is complianted to ieee1149. 4 std, is designed

    本文深入研究了ieee1149 . 4混合信號測試總線及其特點，並根據邊界掃描標準定義的測試結構對混合信號電路的測試方法進行研究，設計出符合ieee1149 . 4標準的混合信號邊界掃描測試系統。
  13. 2 ) for making the meshes consistent on the common boundaries of adjoining surfaces, a new approach of boundary discretization is employed. 3 ) the boundary - representation structure is adopted to fulfill the mesh generation over combined surfaces. 4 ) the quality of surface meshes is improved by point creation on 3d scan lines and diagonal swapping procedure

    通過引入可移動的虛邊界解決了閉合曲面的剖分問題；通過對鄰接曲面公共邊界的統一處理，保證了組合曲面拼合處網格的相容性；以邊界表示數據結構為基礎實現了三維組合曲面的全自動網格剖分；採用空間掃描線布點、診斷交換等技術，優化了網格的質量；並以autocad為支撐平臺objectarx為開發工具，開發了一個基於幾何造型的曲面三角形網格全自動生成程序。
  14. In order to enhance the testability, reduce the maintenance costs of the electronic equipment, it is very important to develop a boundary - scan test system ( bsts )

    隨著具有邊界掃描結構的晶元在裝備中的大量應用，開發出實用的邊界掃描測試系統，對于提高裝備的可測試性，降低維護和保障費用具有重要意義。
  15. The main contents are as follows : the structure of mixed - signal circuit which newly - defined in ieee1149. 4 std is analyzed in detail, especially anolog boundary module and test bus interface circuit. on the basis of mixed - signal boundary scan technology, a scheme of mixed - signal boundary - scan test system is presented and the hardwares are implemented, including the controller and display unit

    主要研究的內容以及所作的工作如下:詳細分析了ieee1149 . 4標準中針對混合信號電路測試新增的結構，即模擬邊界模塊及測試介面電路。基於混合信號邊界掃描技術標準，提出混合信號邊界掃描控制器的設計方案並實現了其硬體設計，包括邊界掃描控制模塊、顯示驅動模塊等。
  16. As a design for test technology, the boundary - scan test fixes a special element called boundary - scan cell ( bsc ) between the device input pins and the core logic inputs, or between the core logic outputs and the device output pins

    作為一種結構插入的可測性設計技術，邊界掃描測試技術將邊界掃描測試單元（ boundery - scancell ， bsc ）插在集成電路內部每一個輸入輸出引腳上。
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