邏輯埠 的英文怎麼說

中文拼音 [luóbù]
邏輯埠 英文
logical port
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 埠 : 名詞1. （碼頭） pier; port; wharf; jetty 2. （有碼頭的城鎮） port city3. （商埠） commercial port
  • 邏輯 : logic
  1. The hardware of the system is composed of a high - speed optical - isolator circuit, a first - in / first - out dual - port memory buffer circuit, a pci interface chip ql5032, and a logic control circuit

    系統的硬體部分是由高速光電隔離電路，雙埠fifo存儲緩沖電路， pci總線介面電路ql5032及邏輯控制電路等組成。
  2. Each server has two logical ports one for each logical partition, namely 0 and 1

    每個服務器有兩個邏輯埠（每個邏輯分區對應一個） ，即埠0和1 。
  3. Our researching work developed a high performance fast ethernet switcher with networking management, which is one of the best solution schemes of fttb ( fiber to the building ) in intelligence uptown. this ethernet switcher can give each terminal user 1 oombps network bandwidth and make two multimode fiber ports bound into a logic port

    本課題研製了一種基於網路管理的高性能快速以太網交換機，該以太網交換機是智能小區的光纖到樓的最佳解決方案之一。該以太網交換機能提供給每一個終端用戶100mbps的網路帶寬，並且能將兩個多模光纖的物理埠捆綁成一個邏輯埠。
  4. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  5. Each of the logical nodes is allocated a communication port

    每個邏輯節點都分配了一個通信埠。
  6. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  7. Aimed at performance improvement for the iocp multimedia network server in large - scale complex environment, this paper presents the methods concerned with network base development, configuration design and the logical module design as follows : elevate data processing efficiency by optimizing the data package and transmission, enhance code reusability and extendibility by modular construction, and further optimize the logical module performance through port dispatch

    摘要面臨iocp多媒體網路服務器所的大復雜度環境設計問題，本文論述該網路服務器的網路底層開發、結構設計及邏輯模塊設計，提出提高其性能的方法：優化數據封裝以及投遞方式，增加數據的處理效率；整體結構模塊化設計，提高代碼的可重用性以及可擴展性；通過埠分流的方式，實現對邏輯模塊性能改進。
  8. Logical port number

    邏輯埠號
  9. Typically, when you draw a dependency relationship between a port and an interface, the dependent requiring interface will handle all the processing logic at execution time

    一般來說，當你畫一個埠和一個介面之間的依存關系時，依賴方（要求）的介面將會在運行時間內處理所有的處理邏輯。
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