邏輯塊號 的英文怎麼說

中文拼音 [luókuāiháo]
邏輯塊號 英文
logical block number
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 邏輯 : logic
  1. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. Chapter three is about the experimental research of the real time optimal position system ( see chapter two ), emphasis on the high performances of 196mx pts interrupt response and safe design of ipm module. the analysis of perfect experimental waveforms and basic algorithm are also provided. chapter four focus on the properties and application of ekf estimator

    論文第三章對點對點快速定位系統進行了實驗研究，重點介紹了196mxpts中斷系統對高速處理實時邏輯信號和消除編碼盤光電頭邊緣振蕩效應所起的作用、 ipm模塊的安全性分析設計等，同時給出了完整的實驗波形分析以及基本演算法。
  4. In the paper we amply introduce the logical structure and design of software and hardware of the virtual multi - channel instrument system for temperature measurement. applying the object oriented programming ( oop ) method, center control module, transmitter demarcating module, channels and scopes module, data collection and process module, data analyze module, data display module, data redisplay module, print module and the other auxiliary functions are designed, which realize the collection, process, analyze and display of the powerful virtual instrument

    在本文中，作者詳細介紹了虛擬式多通道溫度測試儀系統的邏輯結構和軟硬體設計，運用面向對象（ oop ）的軟體設計方法，通過中心控制模塊、變送器標定模塊、測溫通道和測溫范圍設置模塊、數據採集與處理模塊、數據分析模塊、數據顯示模塊、數據回放模塊、列印輸出模塊和其他輔助功能模塊的設計，實現了對溫度信號進行採集、處理、分析和顯示的功能很強的虛擬測溫儀器。
  5. Finally the module is accomplished successfully after installation and debugging. it mainly consists of the minimum system of dsp, a / d conversion circuit, cpld control logic, watchdog circuit, op amplifier and filter circuit

    該模塊主要由數字信號處理器最小系統、模數轉換電路、復雜可編程邏輯器件控制邏輯、看門狗電路、運算放大器電路和模擬濾波器電路構成。
  6. In the hardware design, the analog circuit, high - speed a / d convertor, storage control logic and vxibus interface are discussed. the results of the simulation and analysis of the circuits are given

    在模塊的硬體電路設計部分中，著重對信號調理電路、高速a / d轉換器、高速存儲邏輯控制以及vxi總線介面等內容進行了討論，給出了具體的電路設計和關鍵器件的說明，並對部分模擬電路和數字電路進行了模擬分析。
  7. As modules ， they are black boxes, in the sense that they will perform desired functions when voltage levels, corresponding to logic states, are presented at the inputs

    作為「模塊」 ，它們是一些黑色的盒子。當通電時，它們就能以這種形式工作，對邏輯信號進行處理，並輸出結果。
  8. A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd

    通過高速數據採集模塊將信號數字化，以高性能數字信號處理器tms320vc5402為核心構成數據處理單元，採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元，使用液晶顯示器做為終端顯示設備，構成一個完整的示波表樣機。
  9. While in pratical applications, the esd method still has drawbacks in graphical modeling capability, connections with products " structures, size control of esd models, and etc. through in - depth study of the esd method, this paper systematically describes the framework and its basic modeling elements of esd, explains the principles of risk modeling, gives the mathematical model of the basic modeling elements of the esd framework to support the quantitative analysis of the esd model. based on the research above, this paper expands the esd framework, which includes : to overcome the drawback in graphic modeling capability of the esd method, the paper invents some new logical modeling symbols like " n / k " gate, sequence gate, expandable gate and constraint, those enrich the modeling capability of the esd method. to overcome the drawbacks in connections with products " structures and size control, the paper explains the multi - layered modeling principles based on the esd

    在上述研究基礎上，對esd框架進行了擴展，包括：針對esd圖形建模能力的不足，提出了「 n中取k門」 、 「順序門」 、 「可擴展門」以及「限制」等新的邏輯建模圖形符號，豐富完善了esd的建模元素；針對esd模型與產品結構關聯及規模控制方面的局限，提出了基於esd的層次化建模原理，使得可基於esd進行層次模塊化建模；針對esd與其它安全風險分析技術的綜合運用問題，分別討論研究了與故障樹分析技術、馬爾科夫狀態轉移圖集成的esd ft和esd m方法，提高了esd建模的靈活性；針對動態系統風險評價模型的求解問題，討論提出了運用esd求解動態概率風險評價問題的解析解或近似解析解方法，並予以了示例說明。
  10. At last, fpga designs of symbol and frequency synchronization are completed

    最後在演算法和模擬的基礎上對符號和頻率同步完成了邏輯模塊設計。
  11. As to the software, we firstly scheduled all of the test signal path between the computer and the uut, the output control logic between the digital i / o card and programmable relay key matrix, and used all of this to be the base of software design, then we introduce the block flow of software

    在軟體設計部分首先規劃了所有測試信號在計算機主機與被測件之間的連接和傳輸路徑、數字i / o卡對可編程繼電器開關矩陣的輸出控制邏輯，作為軟體設計依據，隨后介紹了軟體的模塊化設計思想。
  12. The thesis includes the design of hard circuit, pcb ( printed circuit board ), driver and application soft involving a / d board and d / a board. the detailed functional modules consist of multiplex signals select module 、 analog digital conversion module 、 digital analog conversion module 、 pci protocol conversion module 、 driver and magnifying module 、 control logic 、 clock circuit and configuration circuit. the importance of the thesis is a / d board

    本課題包括硬體電路、印刷電路板（ pcb ） 、驅動程序和應用軟體的設計，涉及a / d板和d / a板兩大塊部分，具體的功能模塊包括多路信號選擇模塊、模數轉換模塊、數模轉換模塊、 pci協議轉換模塊、驅動放大模塊、控制邏輯、時鐘電路和配置電路，其中重點是a / d板部分。
  13. This paper projects a utility subdividing drive system of step motor, which consists of digital control module, drive module and power module, it uses at89c52 single chip processor as the core, it realizes the external event or generates control signal by i / o interface, timer and external interruption, the system introduce pld device and isp technology to the design of phase sequencer, it simplified circuit and improved the anti - disturbing capability by using abel - hdl language, this system can realizes data memory, velocity digital control and led display, etc. this paper adopted firstly the single - chip technique to design control system, which replaced old complicated logic control circuit and simplified test process

    本文研究了一種實用的步進電機細分驅動系統，由數字控制模塊、驅動模塊和電源模塊組成，系統以at89c52單片機為核心，通過單片機的i o口、定時器計數器中斷來實現外部事件監控以及控制信號的產生，系統將可編程邏輯器件（ pld ）器件和在系統編程（ isp ）新技術引入到細分驅動環行分配器的設計，通過abel _ hdl語言編程實現硬體軟化設計和邏輯重構，大大簡化了電路，並提高了電路抗干擾能力。使系統實現參數存儲，速度數字控制，數碼顯示，進退刀控制等功能。
  14. A mac unit has been specially optimized and can complete a 32 - bit mac operation within one clock cycle of 5ns. we analyze the multiplication procedures and find out the obstacles to improve the speed. to accelerate the multiplication operation, a modified booth structure has been used to reduce the number of partial products

    在分裂式alu設計工作中，提出了三種方法解決時延問題： （一）具體分析關鍵路徑中決定時延的關鍵信號，優化其相關邏輯電路，提高速度，減小模塊整體關鍵路徑時延。
  15. Finally, on the basis of the mpeg - 1 layer hencoding hardware structure, the block of logic communicates with the pc over the parallel port and the interface for flash memory are design. then a mpeg audio coding system, which applies to store audio signal, is presented through the field programmable gate array device technology

    最後，在mpeg - 1層編碼的硬體結構的基礎上，結合計算機並口通信和flash存儲器的介面模塊，採用現場可編程邏輯器件fpga技術，最終設計了一種應用於音頻信號存儲的mpeg音頻編碼系統。
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