邏輯指令 的英文怎麼說

中文拼音 [luózhǐlìng]
邏輯指令 英文
logands logical commands
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 指 : 指構詞成分。
  • 邏輯 : logic
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  1. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  2. Instruction, control logically flows back to the cli exception handling mechanism

    指令后，控制邏輯上流回cli異常處理機制。
  3. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  4. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  5. The reactive power compensation is an important engineering in the power system. the active reactive power compensator designed in this text takes the instantaneous reactive power theory of three - phase as foundation, and is formed by the reactive current testing circuit, current tracking control circuit and the main circuit, and among them the current tracking control circuit is formed by instruction current arithmetic circuit, current polarity checkout circuit and current tracking control logic circuit three parts in the circuit form

    無功功率補償是電力系統中的一項重要工程，本文所設計的有源無功功率補償器是以三相瞬時無功功率理論為基礎的，它由無功電流檢測電路、電流跟蹤控制電路和主電路三大部分組成，其中電流跟蹤控制電路由指令電流運算電路、電流極性檢測電路和電流跟蹤控制邏輯電路三部分構成。
  6. The author introduces basic requirements, selection and determination of the fighter ' s attack course in air - to - air multi - target attacking, and provides the logic diagram for calculation of the course, aiming deviation and operating command

    摘要介紹了空對空多目標攻擊載機攻擊航線的基本要求、航線選擇和求解方法，以及載機航線、瞄準偏差、操縱指令的計算邏輯圖。
  7. It includes : dynamic show of technics flow, real time data acquirement and show, history data save and print, fault alarm, etc. the plc control system mainly accomplishes the wastewater technics flow control, harmonizes the logical relationship among local intelligent control instruments and transmits the state of each local equipment to the industrial computer simultaneously, the plc control station receives the control commands from the industrial computer ; the local intelligent units take charge of the correlated parameters measure, disposal and control, and it will transmit the related parameters to the computer, etc. in this thesis, introduced municipal wastewater treatment technics, the integrated application program development of computer, the design method of plc control station, the communication between plc control system and computer, and the network of wastewater treatment with profibus - dp was also discussed

    上位計算機主要實現遠程監測和管理功能，具體包括:工藝流程動態顯示、實時數據獲得及顯示、歷史數據存儲與列印、故障報警等功能plc控制系統主要完成工藝流程式控制制以及協調現場各智能儀表之間的邏輯關系，將現場各設備的運行狀態通過通訊網路傳輸到上位計算機，並接收上位計算機的控制指令;現場各智能儀表單元負責各相關參數的監測和處理、控制，並將有關參數送往上位監控計算機進行處理、保存等。本文以莎車污水處理項目為例，介紹了城市污水處理工藝、上位監控計算機的綜合應用程序開發、城市污水處理自動控制系統plc控制站的設計和採用profibus系列中廣泛應用於現場設備的profibus - dp總線。
  8. After all logic events have been completed, the control unit initiates the next instruction fetch.

    在所有的邏輯事件完成之後，控制器再次啟動下一步指令的讀取。
  9. The instruction set includes all the normal arithmetic and logical operations, along with conditional and unconditional branches, load store, call return, stack manipulation, and several special types of instructions

    指令集包含所有的常規算術和邏輯運算，以及條件轉移和無條件轉移、裝入存儲、調用返回、堆棧操作和幾種特殊類型的指令。
  10. Table 5 lists powerpc logical instructions

    表5列出了powerpc邏輯指令。
  11. One supports branch instructions. the other does n ' t. and they both lack features common to general purpose microprocessors such as logic instructions and indirect memory access

    Gcx支持兩類後端，一類不支持轉移指令，另一類支持轉移指令，但兩者都缺乏一般微處理所具有的例如邏輯指令、存儲器間接訪問等特性。
  12. Makes an investigation of interpretive principles and key techniques of plc ladder diagram language based on fx2n series plc instruction set, and proposes interpretive methods of basic program instructions, sfc instructions and application instructions on cygnal f040 single chip system, as well as the design and debugging of hardware and software. 3. analyzes the can controller of cygnal f040

    （ 2 ）針對fx2n系列plc指令集，對plc梯形圖語言的解釋原理和關鍵技術進行了詳細的研究，提出了在cygnalf040單片機硬體系統上實現plc基本邏輯指令， sfc指令和功能指令的解釋方法，完成了其硬體和軟體的設計和調試。
  13. In a computer, a functional unit that interprets and executes instructions. note : a processor consists of at least an instruction control unit and an arithmetic and logic unit

    計算機中，解釋並執行指令的一種功能單元。注：處理器至少包含有一個指令控制器和一個算術與邏輯運算器。
  14. The control unit, which extracts instructions from memory and decodes and executes them, calling on the alu when necessary

    控制單元，從內存和代碼中提取指令並執行他們必須的時候訪問算術邏輯單元。
  15. Firstly, for the purpose of research and verification of multithread microprocessor, a superscalar microprocessor model armp - v2 is built on the basis of armp microprocessor ; secondly, the issue logic is not only the critical path in a superscalar microprocessor, but also critical to the performance of a multithreaded microprocessor with superscalar execution core

    首先，在設計的嵌入式微處理armp的基礎上進行改進，提出了一個超標量處理器模型，用於多線程處理器系統結構的研究與驗證。其次，指令發射邏輯是超標量處理器中的關鍵路徑，也是制約執行單元為超標量結構的多線程處理器主頻提高的關鍵因素。
  16. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  17. We can take dsp to realize fast encryption algorithm because of its highly parallelism, application - specific hardware logic, and application - specific instructions. pci transaction and dsp processing of data can take place simultaneously for its dual - access ram ( daram ) and host port interface ( hpi ). and, the time taken for interruption almost can be ignored because of deep buffer technology

    Dsp具有高度的并行結構、專用硬體邏輯以及許多專用指令，可以實現快速加密演算法， dsp的雙訪問ram （ daram ）和主機并行介面（ hpi ）可以實現數據pci傳送和dsp處理同時進行，另外採用了深度緩沖技術，使花在主機中斷上的時間幾乎可以忽略不計，所以基於dsp的計算機數據加密卡pcijmc2000獲得了較高的處理速度。
  18. The main works were listed below : 1. as the core of image tracker, the advanced dsp technology ( adsp - ts201 ) and the programmable logic device ( ep1s40f1020 chip ) were combined together to make certain that instruction was completed within single instruction period

    主要體現在下面幾點: 1 .圖像跟蹤器的硬體平臺以先進的dsp技術（ adsp - ts201 ）和可編程邏輯器件（ stratix系列的ep1s40f1020晶元）為核心，構成實時的圖像跟蹤處理器，使得指令可在單指令周期內完成運算。
  19. The control procedure in the servo system contains the logical function module, the nc repertoire module and the servo - control module, all these are embedded in the same periods which is 60us

    軟體方面，核心控製程序中內置了邏輯功能模塊、 nc指令模塊、伺服控制模塊，採用了全同期控制，控制周期為60 s 。
  20. The scale, facility, setup mode and the topper application are increasing, but the network management system still adopts a centralizing structure based on manager / agent model. in the centralizing structure, the network management system can ’ t change with the scale and complexity, which made the system bigger and bigger. all management logic is computing in one workstation, that will occupy too many bandwidth, depress performance and made the workstation become the weakest part, if the workstation overrun or dead, agent can ’ t come back because it must wait manager ’ s command

    目前，我國電信網路正處于高速發展中，網路的規模越來越大，設備種類越來越多，組網方式越來越多樣化，應用越來越復雜，但是網路管理系統仍然普遍採用管理員/代理的集中式管理方法，在集中式網路管理模式中，網管系統不能隨著網路規模和復雜度的變化而變化，致使網管系統越來越龐大;網路管理邏輯全部集中在一個管理工作站中計算，需要佔用大量的帶寬來傳輸設備數據，有效性差，同時管理工作站是系統中最脆弱的部分，一旦管理方超負荷或死機，代理方因為必須等待管理方的指令而無法恢復系統，導致系統崩潰。
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