邏輯線路 的英文怎麼說

中文拼音 [luóxiànlù]
邏輯線路 英文
logic arrangement
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 邏輯 : logic
  • 線路 : 1. [電學] circuit; line 2. [交通運輸] line; route
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  3. The detailed works are as follows : the finding patterns problems in the time - series data sequence are described, and a new trend logic expression method is introduced, and its algorithm and experiment result of algorithm are given ; time - scries data are disposed, and using the arctg. slope of line as the sample of pattern recognition, so ignoring the aberrance of pattern in the classified. in addition, a new time - series pattern finding algorithm based on higher - order neural network is put forward

    同時給出了本文的具體的工作，主要是：對在時序數據序列中發現模式問題進行了描述，並介紹了一種新的趨勢邏輯表示方法，給出了其演算法及演算法的實驗結果；對時序數據進行處理，提出了利用線段的斜率反正切值作為模式識別的樣本，從而在分類時忽略模式的畸變；另外，還提出了一個新的基於高階神經網路的時序模式發現演算法。
  4. It integrates the functions of servo amplifier, dynamic operator, position transmitter and remote communication. many new functions have added to its original ones, such as the real - time logical judgment, malfunctions self - diagnosis, alarm & protection, led display, on - line setting and adjustment of functional parameter and position transmitter, power - absence data auto - protection, watchdog system protection, and the long - range communication with pc

    系統集伺服放大器、電動操作器、位置發送器及遠程網路式通信功能於一體，在保留對應部分原有功能的同時，還新增了邏輯實時判斷、故障實時監控、 led動態顯示數據、功能參數設置、掉電數據自保護、 「看門狗」電路保護、位置發送器在線調節、與遠程工控機數據通信等眾多功能。
  5. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  6. In this paper, based on the study of vga graphic displaying theory and the theory of synchronizing display between led large - screen display system and crt image, a method, bit plane addressing method which has good effect -. high ratio of performance to price and can be implemented easily in circuits is discussed. and the principle and the implementation of the multi - gray led display system with programmable logic devices cpld and fpga are analyzed in detail

    本文在分析vga圖象顯示原理和led大屏幕與crt視頻圖像同步顯示原理的基礎上，論述了一種顯示效果較好、性能價格比高、電路上易於實現的方法? ?位平面尋址法實現多灰度圖象，並詳細分析了應用復雜可編程邏輯器件cpld和在線可編程邏輯器件fpga實現多灰度彩色led大屏幕圖像顯示的原理及電路實現。
  7. The research on knowledge - based part logical manufacturing process design, executive manufacturing process design and process route optimization was done, as the definition of the logical manufacturing process and executive manufacturing process are given

    主要研究基於知識的邏輯加工路線設計、可執行加工路線設計及基於物理製造單元的工藝分工優化方法。
  8. Knowledge - based part logical manufacturing process design, as well as the matching method between the logical manufacturing unit and physical manufacturing unit, are given, which provide references for the more complicated process questions

    研究了基於知識的零件邏輯加工路線的設計，邏輯製造單元和物理製造單元的映射方式。這為將來解決更為復雜的工藝問題提供了思路上參考。
  9. Firstly, thesis has been analysed the enterprise present situation, the problem that exists aspect has pointed out the enterprise in the selection in objective market and competitor analyses and positioning etc

    論文是以山東光岳轉向節總廠營銷戰略規劃為主線，按照提出問題、分析問題、解決問題的邏輯思路展開。
  10. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  11. It implements filter groups design, wide range linear automatic gain control design, and the programmed logic device design based on vhdl, and discuss their application in initial radar system in details

    其中包括分段濾波器的設計技術，寬線性自動增益控制agc電路的設計技術，以及基於vhdl語言的可編程邏輯器件的設計技術，並對其在數據採集系統中的應用作了詳細的討論。
  12. First, the author in detail introduces the typology to substitute concept as a systematization method. the typology method not only acknowledges that the legal science about the pure economic loss is still pausing at a starting degree. moreover it has provided the research route as following : experience type - logic type - standard type

    首先，筆者詳細介紹了類型替代概念的體系化方法，作為方法論的自省，類型化不僅承認了法學界對純粹經濟損失的研究程度尚停留在混沌狀態的現狀，而且提供了從「經驗類型」到「邏輯類型」再到「范類型」研究路線。
  13. On basis of the development of modern control technology and apply of the network technology and locale bus - mastering technology ， this text analyzes the essential element for produce of wire - roll mill : principle of assign for speed ; expatiates in detail on the network structure and communication protocol of ethernet and profibus - dp ; concretely describes the forms of control system configuration ， the function and features of its software and hardware designs ; also, introduces mainly control function of control system, ， for example ， sequence control 、 loop control 、 fly shear control and operation and monitor function etc

    基於現代控制技術的發展、網路技術以及現場總線技術的應用，本文分析了線材生產的基本要素：速度的分配原則；分析了工業以太網ethernet和現場總線profibus - dp的結構和通訊協議。主要說明plc控制系統的組織結構形式，系統的軟硬體設計的功能和特點。同時，詳細介紹了控制系統的主要控制功能，如邏輯控制、活套控制、飛剪控制以及操作監控功能等等。
  14. Therefore, it can be named by “ the specific demultiplexer of sdh ”. the design of pos line card was discussed and we also have finished the control logic of the hardware platform of the specific demultiplexer

    論文主要討論專用分接器的pos線卡設計和硬體平臺的控制邏輯電路設計與實現。論文首先對基於fpga的10gbps的pos線卡的設計方案進行了研究。
  15. Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform

    本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。
  16. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  17. In computers, a logic network in the form of an array of input leads andoutput leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  18. In computers, a logic network in the form of an array of input leads and output leads with logic elements connected at some of their intersections

    在計算機中，由輸入線和輸出線陣列形成的一種邏輯網路，在它們的某些交叉點上用邏輯元件相連接。
  19. A study of logical rules of the effect and transfer of smsd aesthetic concept learning

    審美概念學習效應與遷移的邏輯線路探究
  20. This part discusses the issue in two points : one is self reflection, the alienation of film & tv culture ; the other is the focus on campus, on which the value education is being carried out inefficiently

    因此本部分沿著這種邏輯思路從兩個敘述線索展開論述: （一）自身返觀:影視文化的異化， （二）聚焦校園:學校價值觀教育的低實效性。
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