邏輯編號 的英文怎麼說

中文拼音 [luóbiānháo]
邏輯編號 英文
logical number
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 邏輯 : logic
  • 編號 : 1 （按順序編號數） number 2 （編定的號數） identifier; serial number; 編號次序 numeral order; 編...
  1. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  2. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  3. The numbers shall not experience " growing pains " and need to be renumbered

    號碼能耐萬年，邏輯如新，不需一再整編。
  4. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  7. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  8. Chapter three is about the experimental research of the real time optimal position system ( see chapter two ), emphasis on the high performances of 196mx pts interrupt response and safe design of ipm module. the analysis of perfect experimental waveforms and basic algorithm are also provided. chapter four focus on the properties and application of ekf estimator

    論文第三章對點對點快速定位系統進行了實驗研究，重點介紹了196mxpts中斷系統對高速處理實時邏輯信號和消除編碼盤光電頭邊緣振蕩效應所起的作用、 ipm模塊的安全性分析設計等，同時給出了完整的實驗波形分析以及基本演算法。
  9. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  10. Finally the module is accomplished successfully after installation and debugging. it mainly consists of the minimum system of dsp, a / d conversion circuit, cpld control logic, watchdog circuit, op amplifier and filter circuit

    該模塊主要由數字信號處理器最小系統、模數轉換電路、復雜可編程邏輯器件控制邏輯、看門狗電路、運算放大器電路和模擬濾波器電路構成。
  11. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  12. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  13. Tms320c5402dsp was used in the design to replace six scm those was used in the automatic biochemical analyzer now and to control system, cpld epm7128 offer logic circuit to the system. a 16 - bits high - speed a / d conversion device a / d976a replaced a / d574 to complete digital - analog conversion

    本系統設計中採用一片高性能的dsp （數字信號處理器） tms320c5402代替了目前生產的全自動生化分析儀的六個單片機完成系統控制，用可編程邏輯器件epm7128提供所需的邏輯信號，採用16位高速a d轉換器ad976a取代以往的ad574完成模數轉換。
  14. A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd

    通過高速數據採集模塊將信號數字化，以高性能數字信號處理器tms320vc5402為核心構成數據處理單元，採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元，使用液晶顯示器做為終端顯示設備，構成一個完整的示波表樣機。
  15. To build new scps, used to load vpmn service logic so as to build a network of logical circuits on the basis of the plmn, providing the users with functions of dedicated numbering and abbreviated number dialing and taking charge of billing

    新建scp ，用於加載vpmn業務邏輯，以便在公用移動網基礎上建立一個邏輯話路網，給用戶提供專用編號計劃、縮位撥號等業務功能並負責計費工作。
  16. Vpmn service is a service which allows group users to communicate with each other through abbreviated numbering or dedicated numbering plans over a private network of logic voice circuits, based on the public land mobile network ( plmn ) and the public fixed telephone network ( pstn )

    虛擬專用移動網業務（以下簡稱為vpmn ）是在公用陸地移動通信網（ plmn ）和公用固定電話網（ pstn ）上建立一個邏輯話路專用網，通過縮位撥號、專用編號計劃等方式使企業、集團用戶群內進行相互聯系的網路。
  17. Application of cpld in space - time 2 - d radar signal processing

    時空二維雷達信號處理中的復雜可編程邏輯器件
  18. In hardware design, an integrated multi - center a / d chip is for input signal conversion, cpld and arm empu are the core of fault diagnosis system and information processing. host computer is connected with the system through network technology - which owns certain advantages such as wide range of input signal, powerful processing ability and low power consumption ; also it can be extended as a remote portable terminal

    在硬體設計上，採用集成多通道a / d轉換晶元完成輸入信號的轉換，使用大規模可編程邏輯器件和高性能嵌入式處理器作為故障診斷系統控制和信息處理的核心，採用網路技術實現診斷系統與主機的連接，系統具有前端輸入信號范圍寬，處理能力強，功耗低，可擴展為遠程診斷系統便攜式終端等優點。
  19. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  20. 4 lee c y, lu e h, lee j y. bit - parallel systolic multipliers for gf fields defined by all - one and equally - spaced polynomials. ieee trans. computers, 2001, 50 : 385 - 393

    近些年來，有限場數值運算被廣泛應用在編碼理論計算機密碼數字訊號處理，邏輯設計，和隨機數產生器等領域上，受到相當大注意。
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