邏輯處理器 的英文怎麼說

中文拼音 [luóchǔlǐqì]
邏輯處理器 英文
lo logic processor
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 處 : 處名詞1 （地方） place 2 （方面; 某一點） part; point 3 （機關或機關里一個部門） department; offi...
  • 理 : Ⅰ名詞1 （物質組織的條紋） texture; grain （in wood skin etc ） 2 （道理;事理） reason; logic; tru...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 邏輯 : logic
  1. We have implemented a series of algorithm, which includes rule adornment, logic program adornment and factorization, magic transformation, factorizing magic transformation. the platform is characteristic of transplant, expansion

    處理器中實現了本文中用到的一系列演算法，其中包括：規則修飾、邏輯程序的修飾、魔集轉換、邏輯程序的分解、分解的魔集轉換。
  2. Because the switching speed of magnetologic gates is fast, switching at billions of cycles per second ( gigahertz ), this chameleon of processors can alter its functionality many times within the space of even one second

    由於磁邏輯閘的開關速度很快，每秒達幾十億次，所以這種變色龍般的處理器，在短至一秒之內就能多次變換功能。
  3. Nand wafer and micro - controller procurement power : steady and cost effective supply of raw materials

    邏輯晶元和微處理器采購能力：穩定高效的原材料供應。
  4. The processor itself has traditionally required one or more boards of logic.

    處理器本身通常需要一塊或幾塊邏輯板。
  5. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  6. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  7. Business logic in the form of chained message processor components can be easily configured at a fix session level

    即插即用的業務邏輯可在fix對話層簡易配置連鎖式信息處理器組件的業務邏輯。
  8. The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit

    該系統硬體包括數字信號處理器晶元、前向輸入通道、液晶顯示器、模擬量輸出部分、鍵盤輸入部分、保護電路部分和邏輯控制部分。
  9. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  10. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  11. The ina128 is used by left leg ' s driver circle and the aims are to enhance the cmrr and reduce the disturbance of 50hz. the part of a / d transmitting chip is the adc0809 which have a eight - channel transmitter, a eight - bit a / d transmitter and the logical control by microprocessor

    考慮到家庭監護的實際應用，精度的要求不是很高， a / d轉換器採用的是adc0809 ，它有8通道多路轉換器、 8位模/數轉換器和與微處理器兼容的控制邏輯電路。
  12. The element - available ( ) function returns a boolean value that indicates whether the element specified is supported by the xslt processor

    函數的作用是：返回一個邏輯值，用於指定xslt處理器是否允許支持指定的元素。
  13. The transistors in this configuration would also be used to amplify the small currents needed to read a magnetoresistive bit [ see box on page 63 ]

    這些排列好的電晶體也會將微小的電流放大，這樣才能讀取磁阻位元（見83頁磁邏輯處理器） 。
  14. In addition, some interface circuits, such as high - power d / a card, filter board, logic - process board and the feature of cvi programming language and windows programming are also introduced in detail with some chapters

    後面章節詳細介紹了系統的一些介面和控制電路，如大功率數模轉換板、濾波器、控制邏輯處理器等等，以及cvi工業控制軟體開發環境及windows編程等軟體方面的內容。
  15. In order to cope with existing fuzzy inference processors, a dedicated hardware is designed to tackle the interface

    ?了能與既模糊邏輯處理器溝通，我們提出了一個硬體介面以動態產生歸屬函數。
  16. The basic idea behind our approach is to simplify the representation of membership function without affecting the precision of fuzzy computation or slowing the speed of fuzzy inference

    我們基本的想法，是要簡化歸屬函數的表示法，但不影響模糊計算之準確度，亦不影響模糊邏輯處理器進行模糊推論所需的時間。
  17. The framework consists of four function modules, i. e., presentation module, controller module, business logic module, data manipulation module. through separation of the interface and implementation, the system structure becomes clear, and the maintenances is easier

    論文詳細介紹了框架的四個功能模塊，分別是表示層模塊、控制器、商業邏輯處理模塊和數據操作模塊，通過功能的分離和功能包裝，使得系統的結構清晰，後期的維護工作變得容易。
  18. Faced with this problem, software architects can choose to divide the server s business - logic processing and user - interface processing onto separate tiers on separate machines

    面對該問題，軟體設計者可以選擇將服務器的業務邏輯處理和用戶界面處理劃分到單獨計算機上的單獨層上。
  19. This system passes through a period of time ' s apply, the result indicates that enterprise credit report system adopts struts frame technology has big superiority in both empolder and after empolder. one side the web apply system based on struts frame can divide the apply logic, transact process and display logic into different module to realize. so the thought clear in empolder process, divide the work definitely and boost the whole item empolder ; on the other hand enterprise credit report system adopts j2ee technology empolder b / s apply pattern, so that it depresses the cost sufficiently, improves the utilize rate of server and depresses the demand of client machine

    該系統經過一段時間的應用，結果表明，徵信上報系統在採用struts框架技術開發中和開發后的應用方面都具有較大的優越性。一方面基於struts框架的web應用系統的開發能夠將應用邏輯、處理過程和顯示邏輯分成不同模塊加以實現，做到開發過程思路清晰、分工明確，達到共同推進項目整體開發的目的;另一方面企業徵信上報系統採用j2ee技術開發b / s的應用模式，這樣可以充分的降低成本，提高服務器的利用率、降低客戶機的要求。
  20. In order to develop the product networked marketing and customize system for electric gauge and controller manufacturing enterprises, in this thesis we study on several key technologies. they are data - base technology 、 business logic technology and the realization of client technology

    為了開發計控電器生產企業產品的網路化銷售與定製系統，論文圍繞系統開發中的核心技術問題，進行了系統數據庫技術、業務邏輯處理技術、客戶端實現技術等相應關鍵技術的研究。
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