部分寄存器 的英文怎麼說

中文拼音 [bùfēnjìcúnqì]
部分寄存器 英文
component register
  • 部 : Ⅰ名詞1 （部分; 部位） part; section; division; region 2 （部門; 機關或組織單位的名稱） unit; mini...
  • 分 : 分Ⅰ名詞1. （成分） component 2. （職責和權利的限度） what is within one's duty or rights Ⅱ同 「份」Ⅲ動詞[書面語] （料想） judge
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 部分 : （整體中的局部或個體） part; section; portion
  1. Because no drive software is needed in using chip 21154, this paper don ’ t refer to the drive design. after configuring the register in initialization rightly, the work about design of add - in card are all done

    因為橋晶元不需要驅動軟體，因此不需要進行驅動程序的設計，只需要在初始化的時候對配置寄存器進行正確的配置即可，這些工作在最後一部分完成。
  2. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  3. Every segment register has a “ visible ” part and a “ hidden ” part

    每個段寄存器都「可見段」和「隱藏段」兩個部分組成。
  4. Information technology - international standardized profiles fvt2nn - virtual terminal basic class - register of control object type definitions - fvt2114 - terminal signal titles control object

    信息技術.國際標準數據區fvt2nn .虛擬終端的基本分類.控制對象類型定義寄存器.第16部分: fvt2114 .終端信號標題控制對象
  5. Here a delaying - allocation optimizing strategy is proposed, it adopts a coarse - grained adjustment of the stack frame. at the call site allocations, the caller ’ s stack frame is reduced according to the actual usage while the callee only be allocated a limited stack frame, consequently, the potential spill is reduced to the best advantage

    本文提出一種基於延遲分配的棧寄存器分配策略，為了減少額外代價，採用粗粒度的棧幀調整策略，在調用點處使用alloc指令調整調用者的棧幀大小，並為被調用過程分配部分棧幀，在調用點處從調用者和被調用者兩個角度盡量縮減各自的棧幀，從而減少棧幀的溢出。
  6. The goal of this thesis is to accomplish base - band channel coding / decoding, fh framing / de - framing and fh synchronization, and also to control the modulator and demodulator in the prototype system. all these functions are implemented with a tms320vc5409 dsp

    作為項目的一個重要組成部分，本文採用dsptms320vc5409實現了基帶處理部分的通道編解碼、跳頻意義的組拆幀和跳頻同步、並對調制解調晶元讀寫寄存器進行了配置。
  7. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  8. The configuration that uses ieee - 13 94 to control a vxi system is introduced. chapter 2 describes the resource manager application of message - based device 13 94 - vxi controller and the mechanism of register - based device arbitrary waveform generator ( awg ). the key technology of interface circuit and direct digital synthesis in awg module is discussed explicitly

    本文先對vxi總線技術進行了概略的介紹，在此基礎上，對一具體的vxi寄存器基任意波形發生器模塊進行展開，介紹了任意波形發生器模塊與vxi機箱背板總線通訊的介面電路部分及波形發生機理的核心部分的直接數字合成技術。
  9. Chapter five discusses the design and the process of the generation of the control function, including counter, accumulator, comparator, shift register, demultiplexer, collector, access record. chapter six gives some advice and opinions on how to improve this computer software

    其次介紹了計數器、累加器、比較器、多路輸出選擇、移位寄存器控制項；數據類中的收集器、訪問記錄/部分輸出記錄等控制項的功能介紹和編程思路以及使用實例第六章對平臺的完善和改進闡述了一些個人的建議和想法。
  10. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  11. This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary

    本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。
  12. Information technology. international standardized profiles fvt2nn. virtual terminal basic class. register of control object type definitions. part 2 : fvt213, fvt214. sequenced and unsequenced terminal control objects. european standard en isp 11185 - 2

    信息技術.國際標準輪廓fvt2nn .虛擬終端基本類型.控制目標類型定義的寄存器.第2部分: fvt213 ， fvt214 .連續和非連續終端控制目標
  13. Some variations of this instruction format use portions of the target and source register operand specifiers as immediate fields or as extended opcodes

    這一指令格式的一些變種使用部分目的和源寄存器操作數說明符作為立即欄位或作為擴展的操作碼。
  14. In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io

    在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。
  15. Provides local and global optimizations, automatic - register allocation, and loop optimization

    提供局部優化和全局優化、自動寄存器分配和循環優化。
  16. One was adjusted by built - in register, and the other was adjusted by external variable resistor

    針對vcom調節方式，分別設計了由ic內部寄存器軟體調節和外部可調電阻調節法兩種電路。
  17. An option provided for most load and store instructions is to update the base register in other words, ra with the data s effective address generated by the instruction

    用指令生成的數據有效地址來更新基址寄存器（也就是ra ）是大部分加載和存儲指令的一個可選項。
  18. This paper presents an architecture based - on shift register array, which can be used for the search for the two search pattern simultaneously. this architecture was inspired by the vlsi architecture for diamond - search - pattern - based algorithms. it exploits the overlap of reference data among the search points to reduce data memory accesses which are the most power consuming operations

    其基本思想是利用搜索點之間的參考數據重疊的特徵，把需要用於多個搜索點計算的參考數據存儲在移位寄存器陣列中，通過移位操作來滿足不同搜索點的計算需要，大大降低了數據存儲器訪問次數，從而減少了運動估計中功率消耗最大部分的操作。
  19. Intrinsic functions that do not allocate stack space and do not call other functions can use other volatile registers to pass additional register arguments because there is a tight binding between the compiler and the intrinsic function implementation

    由於編譯器與內部函數實現之間存在緊密的綁定，因此不分配堆棧空間且不調用其他函數的內部函數可以使用其他易失寄存器來傳遞附加的寄存器參數。
  20. A storage which works as though it comprised a number of registers arranged in a column, with only the register at the top of the column connected to the rest of the storage

    一種由許多縱向排列的寄存器所組成的存儲器，只有經頂部的寄存器才和這個存儲器的其餘部分相連通。
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