鎖相環 的英文怎麼說

中文拼音 [suǒxiānghuán]
鎖相環 英文
phase lock loodpll
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  1. The results of experiment tell it is an effective method of share current. a strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase - lock loop to track synchronization signal

    在同步控制上,應用了「優先與搶占」的方式產生同步信號,純硬體實現,簡單可靠;使用了成熟的數字鎖相環來跟蹤同步信號。
  2. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型,利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬,模擬結果顯示,在1 . 5v電源電壓下,頻率為200mhz的參考輸入信號,輸出中心頻率為800mhz ,分頻電路採用4分頻,路帶寬為10mhz ,捕獲時間大約為0 . 92 s ,功耗大約為15mw ,達到了設計指標。
  3. A 45 48 mhz pll frequency synthesizer for cordless phone receiver

    接收機鎖相環頻率合成器
  4. The core instrument for frequency - following is the pll. the dsp is used to realize the regulating of the dead time on - line

    鎖相環作為頻率跟蹤的核心器件,根據最佳死區的理論,用dsp實現死區的在線調節。
  5. In the next place, by studying the change of the resonant frequency of the whole system, this paper designs the circuit to track the resonant frequency of the system by cd4046 mainly. at the same time, in order to improve the efficiency and get better dynamic capability of the converter, we choose pll and fuzzy control after comparing the pll circuit, fuzzy circuit and pll ? fuzzy control circuit. in the end, this paper brings forward the control blue print to realize the drive control circuit of the high frequency converter, using the dsp chip as the key part to realize four routes of pwm drive pulses with dead band of the control system

    其次,通過對整個系統諧振頻率變化的分析和研究,設計了以鎖相環cd4046為核心的鎖相環控制電路,同時,在綜合比較鎖相環控制、模糊控制以及模糊控制和鎖相環復合控制三種控制演算法的基礎上,進行了系統模擬,得出採用復合控制可使跟蹤電路既具有鎖相環路較好的穩態性能,又擁有模糊控制較好的動態性能,系統魯棒性能好,同時也提高了逆變器的效率。
  6. Monitor apparatus can measure valid value of three phase voltage and current, power factor, three phase disequilibrium, instant flecker of short time and harmonic without twenty, degree and harmonic distortion total. the paper are laid on the following. ( 1 ) master plan and function of circuit, ( 2 ) hardware design including circuit and principle of a / d conversion, phase lock, liquid crystal display and keystroke and so on, ( 3 ) design of system software including digital filtering, fft, a / d conversion and monitor interface of pc, ( 4 ) system test

    監測儀能夠完成包括三電壓、三電流的有效值、功率因數、三不平衡、電壓短期閃變、以及20次內的諧波、諧波位、諧波失真總量等的測量。論文重點介紹了以下幾部分: ( 1 )電路的總體設計和功能; ( 2 )硬體設計,包括a d轉換、鎖相環、液晶顯示和按鍵輸入等原理和電路。 ( 3 )系統軟體設計,包括a d轉換、 fft 、數字濾波等程序的原理和演算法以及上位機監控界面的設計; ( 4 )系統測試。
  7. Design of hardware consists of three pll loops, micro wave sample mixer, fractional - n frequency divider

    硬體電路包括三個鎖相環,取樣混頻器,分數分頻器的設計等。
  8. In allusion to the working characteristics and technical difficulties of 155mb / s burst mode receiver, we have put forward to the quick synchronization of inpouring phase locked loops ( pll ). for receiving burst signal, we introduce the scheme of dc coupling and dynamic threshold decision

    針對155mb s突發式收發模塊的工作特點和技術難點,我們提出了注入鎖相環法的快速同步技術;對于突發式信號的接收,我們採用了直流耦合和動態閾值判決的技術方案。
  9. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式( 16qam和4 - qpsk )進行了模擬工作並給出了模擬結果,同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試;然後在基於軟體無線電思想的數字處理平臺(該數字處理平臺實現了中頻數字化)上用dsp軟體完成了載波的位跟蹤。
  10. Pll - qpsk, phased - locked loop quadrature phase shift keying

    鎖相環移鍵控
  11. Pll - qpsk phased - locked loop quadrature phase shift keying

    鎖相環移鍵控
  12. As rs ' s monitoring and control system based on ifix

    基於高性能鎖相環的頻率控制系統
  13. This paper illuminates theory, structure, spectrum distribution, merits and defects, especially spurs of direct digital synthesis ( dds ), and it then introduces phase locked loop ( pll ) theory

    對dds的結構、優缺點、頻譜分佈,特別是雜散性能進行了詳細的闡述。接著,又介紹了鎖相環( pll )的原理。
  14. Bicmos pll frequency synthesizer for uhf receiver

    4106的鎖相環頻率合成器設計與實現
  15. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於位控制技術的時鐘恢復系統。
  16. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll (延遲鎖相環)實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  17. The carrier wave is modulated directly by the baseband signal at several frequency point in l band and s band. firstly, this paper clarifies the theory of i / q modulation, elaborates evm and acpl, and analyzes the effect of amplitude and phase unbalance and dc offset on evm. secondly we review the basic principle of phase locked loop and it ’ s composing parts, including the basic conception and design method of pll frequency synthesizer, especially introduce the charge pump pll frequency synthesizer in detail

    首先,在闡述i / q正交調制基本原理的基礎上,通過對誤差矢量和鄰近通道功率泄漏的詳細分析,定性、定量地討論了各種非理想電路因素(如位不平衡、幅度不平衡、直流偏差等)對調制器性能的影響;其次,介紹了鎖相環的工作原理和基本組成部分,包括鎖相環的設計和路濾波器的設計,特別詳述了電荷泵頻率源;第三,介紹了採用直接調制技術模擬衛星信號的射頻前端的設計;最後,對整個直接射頻調制系統進行測試,結果基本上達到了課題要求。
  18. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影( dsa )成像系統的組成結構和數據流向進行了深入研究和分析,並對系統中的數據流向進行了完整的歸納和總結,給出了x線數字成像系統中的高速大容量數據通道的設計方案;在對sdram的控制方式做了深入探討后,給出了實現大容量多條sdram共同工作的解決方案,在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲;通過對pci總線介面的深入研究,優化後端狀態機設計和低層驅動程序開發,給出了完整的pci介面方案實現高速dma數據傳輸,完全可以滿足視頻傳輸要求;深入研究了基於大規模可編程器件的數字系統設計方法,針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點,提出了利用fpga中的鎖相環提供多個時鐘移的信號來提高系統穩定性的解決方案,從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  19. This paper has launched exhaustive analysis and study to every module of pll and its key part ( vco ) is also improved. the history of phase - locked technology and the actuality of research on it are introduced. and then beginning with the fundamental principles of a phase - locked system, we build the mathematical model based on the architecture of the traditional analog pll, and afterwards investigate some of its characters such as tracking, acquisition, noising, and stability

    本文在對技術的發展歷史和研究現狀調查研究的基礎上,從系統的工作原理入手,分析了鎖相環的數學模型,並以此為出發點對其跟蹤性能、捕獲性能、穩定性及噪聲性能等性能進行了較為深入的研究,對路的各項參數指標進行了詳細的推導,得出了鎖相環數理分析的普遍結論。
  20. The merits of dds such as super fine frequency resdutlon 、 high frequency accuracy 、 easy programmed can be in combination with the excellent character of narrow - band tracing filter merits of pll

    它可以將dds的超高頻率解析度、高頻率精確度、容易實現程式控制等優點與鎖相環良好的窄帶跟蹤濾波特性結合。
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