鐘時序數 的英文怎麼說
中文拼音 [zhōngshíxùshǔ]
鐘時序數
英文
clock-hour figure-
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo
本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation
再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation
並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system
針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。3. with time series simulation software, the cpu ’ s i / o ports simulate i2c bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices
3 、採用軟體模擬時序使cpu的i / o口模擬i2c總線，實現了單片機與時鐘晶元、溫濕度傳感器、存儲晶元等器件的數據交換。We present two different frameworks to analyzing the high frequency time series : first, regularly spaced sampled observations, which is sampled with interval of one hour, one minute even one second ; secondly, the irregularly spaced data, such as transaction by transaction data 。 the main work and innovations of the dissertation include : 1. through empirical research of high - frequency time series of shanghai composite index, the paper researches the different statistical properties on different frequency
高頻時間序列的分析與建模是金融計量學的一個全新研究領域。金融市場中高頻時間序列分為兩類:一類是采樣間隔相等的數據，比如一小時、十分鐘、五分鐘、甚至是以秒為單位採集的按時間先後排列的等時間間隔的數據;另一類是指對交易過程實時採集的數據，也就是每筆交易的數據（顯然是不等間隔的數據） 。Continuing, this paper has detailedly presented all writer have achieved works, which involve designing and implementing audio data assignment func tion, software on - line upgrade function, real time clock driver programme, user input process function, and testing the terminal ' s interoperability with some other h. 323 devices
接著，介紹了作者完成的工作：設計實現了語音數據調度功能、軟體自更新功能、實時時鐘驅動程序和用戶輸入處理功能，以及終端與其它相關的h 323設備的互通測試。Make clear the procedure of sending and receiving packet of kernel and the implementation of traffic control. the special mechanism in linux such as wait queue, task queue, time interrupt is also explained. after analyzing the file system of linux at large, we bring forward the design of modifying of file system. since many little file is created during the service of email and file service, we introduce the non volatile random access ram, by modifying the arithmetic of file system, changing the data flow of file system
本文詳細介紹了針對網路專用服務器的專用linux系統的設計，對linux文件系統進行了詳盡的解析，包括vfs的實現， buffercache的作用等；並對塊設備驅動程序在內核中各個介面進行了分析；解析了內核接收和發送數據包的全過程以及流量控制在內核中的全過程；並對linux系統的一些特殊的機制如等待隊列，任務隊列，時鐘中斷等進行了詳細的解釋。However in soc or high performance cpu an in - chip high quality clock is required to guarantee the timing of all chips
而soc或者高端的cpu一般都採用同步的數字電路設計，時鐘是整個晶元時序的保證。For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion
其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。According to the reserved scanning address sequence, channel range and trigger mode, it can sample data. the module can change sample time and sample length. the sample data can be disposed by the cpu on board and then be stored in 64k ram
本模塊可根據預先設置的掃描地址序列、通道量程和觸發方式進行數據採集，采樣時鐘和采樣長度可以改變，測得數據經過板上cpu的實時處理后在64k的存儲器中緩存。This paper analyze the architecture of amex86 microprocessor, including the analyzer of instruction system, addressing mode, scheduling and clock of instruction, the integration and validation of amex86 architecture. this paper mainly discusses the design and realization of data path and instruction decoder in detail
本論文將對amex86體系結構的微處理器進行體系結構分析，包括指令系統的分析、尋址方式的分析，指令時序以及指令時鐘拍數的分析和amex86系統的集成及驗證等。Software framework is put forward based on the technical programming the cmos / real timer clock, adopting vtoolsd to programme vxd and real - time position control of servo electromotor is realized. so the key problem of developing nc in the windows is solved
該系統的軟體結構通過對系統cmos實時時鐘（ rtc ）編程實現高精度定時硬體中斷，利用vtoolsd編寫了虛擬設備驅動程序（ vxd ） ，實現了對伺服電機的實時位置控制，從而解決了在windows環境下開發數控系統的關鍵問題。At the base of earnestly analysis to the ov7620 working sequence, using its frame synchronization, field synchronization and the pixel - clock signal, completed gathering of the active power meter reading image which is reduced resolutions at the control of mcu
在仔細分析ov7620工作時序的基礎上，利用其幀同步、場同步和像素時鐘信號，在單片機的控制下完成了對電度表讀數圖像的降低解析度採集。The thesis includes the design of hard circuit, pcb ( printed circuit board ), driver and application soft involving a / d board and d / a board. the detailed functional modules consist of multiplex signals select module 、 analog digital conversion module 、 digital analog conversion module 、 pci protocol conversion module 、 driver and magnifying module 、 control logic 、 clock circuit and configuration circuit. the importance of the thesis is a / d board
本課題包括硬體電路、印刷電路板（ pcb ） 、驅動程序和應用軟體的設計，涉及a / d板和d / a板兩大塊部分，具體的功能模塊包括多路信號選擇模塊、模數轉換模塊、數模轉換模塊、 pci協議轉換模塊、驅動放大模塊、控制邏輯、時鐘電路和配置電路，其中重點是a / d板部分。Four benchmark test sequences was used for the simulation, and the average number of cycles required to process a frame of the proposed architecture and average number of reference memory access required per frame has been computed
本文用四個標準測試序列對所設計結構進行了模擬實驗，統計了該結構平均完成一次塊匹配的時鐘周期和平均處理一幀需對參考塊數據存儲器的訪問次數。The relationship between the clock jitter and the sampling sequence of a sine wave is studied, and a new method to measure the jitter and distribution of a clock signal with pico - second resolution is proposed using adc sampling based on estimating method of the parameters in sine signal
摘要研究了時鐘抖動與正弦信號的采樣序列之間的關系，並在正弦信號參數估計法的基礎上，提出一種利用adc采樣測量皮秒量級的時鐘抖動大小和分佈的新方法。Data mapping, command interaction and simulation synchronization are the three main functions. it is unnecessary to recompile the middleware program when different numerical models run in the middle using xml as the format of the configuration file format about matlab numerical models
使用xml作為數值模型的配置文件格式，無需重新編譯中間件程序就可以支持不同數值模型的模擬運行;使用可調的讀取數據時鐘，最大程度地降低matlab數值模擬和hla分佈模擬之間的耦合。The paper is composed by three parts ; we ' ll introduce the background of ic design in the first part, which also covers the developing in domestic and foreign industry ; the whole flow of digital ic backend design will be presented detailed in the second part ; the last part will summarize the paper, as well as discuss the future work
這篇論文主要包括如下三個部分:第一部分為緒論，主要關于國內外行業相關背景，以及課題背景;第二部分為數字後端設計開發過程，分為設計的初始化，時序設置，晶元布局，標準單元擺放，時鐘樹綜合，繞線，物理驗證。分享友人