電控時鐘 的英文怎麼說

中文拼音 [diànkòngshízhōng]
電控時鐘 英文
electrically controlled clock
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 控 : 動詞1 （告發;控告） accuse; charge 2 （控制） control; dominate 3 （使容器口兒朝下 讓裏面的液體慢...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 電控 : drive-by-wire
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronisation of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號
  2. Maintaining a caesium beam clock as the hong kong time standard and providing time signals for radio broadcasts, automatic telephone answering service and synchronization of clocks via internet

    操控銫原子鐘作為香港的時間標準，以及透過各電臺、自動答覆電話查詢服務及網際網路校對時鐘服務提供報時訊號；
  3. Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops

    為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。
  4. Electric - controller is nubbin in developping. we are based on designing to structure of circuit, we are dead against in time and stabilization for controlling and communications, precision and rapidity for transformation etc. we have completed to select on microprocessor, clock - frequency and a / d transfer. it carry out transformation for valve position signal, and select on solid - switch ac

    在控制器的電路結構設計的基礎上，考慮到通訊、控制的及時、穩定、轉換的精度和速度等幾方面，主要完成對微處理器的選擇、時鐘頻率和a d轉換器的選用，閥位變送功能的實現，固態交流開關和顯示器的選擇等。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  7. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  8. The rtc power of the controller is supplies by super capacitance, and the rtc can run for 3 days when power cut, if the power cut time is over 3 days, you may adjust the rtc again

    控制器內部實時鐘採用超級電容供電，在停電后能保持實時鐘運行三天，如果停電時間超過三天，可能要重新校準實時鐘。
  9. In the project, the work completed by the author is as followed : ( 1 ) answer for events " transmition, which are transmitted to application programs, and correspondly dealt ; ( 2 ) answer for all of the handware drivers, included lcd display driver, flash driver, e2prom driver, sound driver, gsm status monitorer driver, keyboard driver, uart driver, real - time controller driver, hung - up monitorer driver ; ( 3 ) answer for all problems related with hardware drivers ; ( 4 ) answer for the tools for write data to flash, such as programs, font libraries

    該項目中，本人完成了以下幾方面的工作： （ 1 ）負責所有消息的驅動，使上層應用程序能夠接收到底層硬體設備產生的消息，並做相應處理； （ 2 ）負責所有硬體驅動程序的設計和調試。驅動程序包括lcd顯示驅動、 flash驅動、 e ~ 2prom驅動、聲音驅動、 gsm模塊狀態監控驅動、鍵盤驅動、串口驅動、實時鐘驅動、電源管理、摘掛機檢測驅動，共10部分。 （ 3 ）負責解決遇到的所有與驅動相關的問題。
  10. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  11. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  12. Plc, robot and cad / cam are called the three major pillars in the modem factory automation. plc, as the head of the three, has become the leading basic automatic equipment in the field of the industry control in the early 1980s " but as a matter of fact, plc being with the lack of friendly man machine interface, rnakes no close relationship between human and machineometimes it even can not be promoted and applied in some fields aiming at the situation mat those imported products are too expensive while domestic products are of rare famous brands, a plc man - machine interface - plc monitor is developedthis paper systemically introduces the developing procedure for the whole system, including how to design hardware and software system. especially emphasizing plc communication protocol. real time message accessing, lcd controller instruction set, definition of data construction for message & tag screens and how to display thern, assignment of internal resource of cpuealization in software among plc & manitor, file format defining a nd download of user data, etcplc monitor will compensate some weakpoints of plc, and extend the application rangeimultanneously enhance the performance of plc and increase the attached value of mechanical machines, undoubtedly it will see hight market prospect

    針對人機界面進口產品的高昂價格和國產品牌稀少的這一現狀，研製開發了一種plc人機界面? plc監控器。本文系統地介紹了整個系統的開發過程，包括硬體系統、軟體系統的設計及實現，重點介紹了plc通信協議，監控器的基本工作原理以及期望實現的功能，監控器電源電路、 sram存儲器掉電保護電路、 cpu監控器電路、按鍵輸入電路的設計及按鍵狀態的讀入，時鐘信息的設定與讀取， cpu液晶顯示器指令系統，信息畫面及標簽數據結構的定義及顯示方法， cpu內部資源的分配，監控器與plc通信的軟體實現，文件格式的定義以及畫面數據的下載等。 plc監控器彌補了plc一些方面的不足，可以擴大plc的應用范圍，提升機械設備的檔次，增加設備的附加價值，具有一定的市場前景。
  13. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  14. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  15. The signal collecting system of singlechip collects the signals from generator. the paper introduces the every part of the singlechip. the key component is a 8051cpu, its surrounding circuits include dc power source, simulating signal collecting circuit, digital signal collecting circuit, a / d converting circuit, clock generating circuit, counting frequency circuit, controlling circuit, communicating circuit, and some other circuits

    前臺單片機採集系統完成對發電機組多信息量的採集，本文詳細介紹了電路設計，系統的核心器件為8051cpu ，其外圍電路包括電源電路、模擬信號採集電路、 a d轉換電路、數字信號採集電路、時鐘發生電路、測頻電路、控制電路、通訊電路等。
  16. The designing of single - chip electronic clock

    單片機控電子時鐘的設計
  17. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  18. The third, according to the aforementioned project, a hardware system is provided which includes the core chip - tms320dsc21 ( ti special dsp ) and its peripheral circuits ( clock and power supply ), video input module, network output module, alarm module, and cradle head control module. the design and debug of hardware system is finished

    接著以ti公司的專用dsptms320dsc21為核心，進行了嵌入式網路攝像機的硬體設計，硬體部分包括： dsc21核心及相關電路（時鐘、電源和調試電路） 、視頻輸入模塊、視頻數據網路輸出模塊、報警模塊和雲臺控制模塊。
  19. In fact, it is more effective in system level. low power technique of microprocessor is composed of clock - gating, close part of cache, and dvs ( dynamic voltage scaling ). low power technique of peripheral equipments design is composed of closing the idle parts of the equipment and degrading the service quality satisfied with lowest requirement

    處理器的低功耗設計大都採用系統級，其技術主要包括:門控時鐘技術， cache部分關閉技術，動態電壓縮放dvs （ dynamicvoltagescaling ）技術;外圍設備低功耗設計包括:關閉設備空閑部件;在滿足基本性能要求前提下，降低外圍設備的服務質量。
  20. To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation

    為抑制時序電路中的冗餘現象，研究了時序電路的門控時鐘技術，並利用t型觸發器進行時序電路設計。
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