電路襯底 的英文怎麼說

中文拼音 [diànlùchènde]
電路襯底 英文
circuit substrate
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 襯 : Ⅰ動詞1 （在裏面托上一層） line; place sth underneath 2 （陪襯; 襯托） set off Ⅱ名詞（襯在裏面的附...
  • 底 : 底助詞（用在定語后, 表示定語和中心詞之間是領屬關系, 現在多寫作「的」）
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Among various fabrication techniques of thin film, the sol - gel process has gained much interest for the preparation of pzt thin film, due to ihe advantages of good homogeneity, easy control of composition, low in - ill i reaving temperature, easy formation of large area thin films pb ( zrxti : - k ) 0 :, ( pzt ) films were prepared on the ito coated glass plates and low resistor silicon wafer in sol - gel dip - coating process associated wi di heat treatment : at different temperatures and characterized by x - ray diffraction ( xrd ) and transmission electron microscopy ( tem ). lt is shown that the pzt ferroelectric thin films with ( 110 ) preferred orientation and well - crystallized perovskite structure can be obtained after annealing at 680 ? for 30 minutes on ito substrate and at 800 " c for lornin on silicon substrate

    Pzt的制備方法有很多，其中溶膠?凝膠（ sol - gel ）方法可以和集成電路（ ic ）光刻工藝相互兼容，處理溫度低，有大面積塗敷性能，能精確地控制組分，無需復雜的真空設備，成本低廉，所以對于集成鐵電薄膜電容的應用這種方法有很廣闊的前景。本文利用sol - gel技術在摻錫的in _ 2o _ 3透明導電薄膜（ ito ）襯底和低阻硅襯底上成功地制備了pzt鐵電薄膜。運用了x射線衍射， sawyer - tower電路和lcr電橋分別對薄膜的晶化溫度，結構和電學性能進行了測試。
  2. Gaas crystal is a kind of iii - v group compound semiconductor material with good electrical performance. the semiconductor devices and integrated circuit ( ic ) fabricated on gaas substrate have such advantages of hign - speed information processing that they have drawn the researcher ' s attention

    Gaas晶體是一種電學性能優越的-族化合物半導體材料，以其為襯底製作的半導體器件及集成電路，由於具有信息處理速度快等優點而受到青睞，成為近年來研究的熱點。
  3. A silicon - based photo - diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging

    在同一襯底上製作了基於同一工藝的光電二極體與接收機電路，以消除混合集成引入的寄生影響。
  4. A novel method for reducing the substrate - rated losses of integrated spiral inductors is presented. the method is that directly forming pn junction isolation in the si substrate to block the eddy currents induced by spiral inductors. the substrate pn junction can be realized in standard silicon technologies without additional processing steps

    提出了一種新的方法來減小硅襯底損耗提高集成電感的q值：在硅襯底形成間隔的pn結隔離以阻止渦流減少損耗，這種方法工藝簡單且與常規硅集成電路工藝兼容。
  5. 4. the noise of the substrate and the inductors of the pads are investigated in detail

    4 .研究了襯底噪聲和焊盤寄生電感對電路的影響。
  6. We studied the resurf, trench - gate, 3d - resurf ldmos. we designed the power switch ic based on epitaxial simox substrate, satisfying the requirements of the user. this ic can sustain 60 ~ 80v shutdown voltage overshot

    在此基礎上，本文設計了性能滿足用戶要求的，基於esoi襯底結構的功率開關集成電路，該集成電路可承受60 ~ 80v的反向過沖電壓，並具有過流，過壓等保護電路。
  7. Liquid encapsulated czochralski ( lec ) si - gaas is widely used in the microwave device and the substrates of high speed digital optic - electronic integrated circuits, and it has become one of major materials in information industry

    液封直拉法生產的半絕緣砷化鎵單晶（ lecsi - gaas ）被廣泛用於微波器件和高頻集成電路的襯底材料，成為當代信息產業的重要材料之一。
  8. The n / n + and p / p + epitaxial structures, which become popular with the development of coms technology, because they can avoid the latch - up and a softerror of ulsi while they combined with the intrinsic gettering ( ig ) technique

    Coms工藝中普遍採用n / n ~ + 、 p / p ~ +的外延結構，這種以重摻雜矽片為襯底的外延結構與內吸雜工藝相結合，是解決集成電路中的閂鎖效應和粒子引起的軟失效的有效途徑。
  9. The accelerometer which has simple fabricated process and high sensitivity and small parasitic capacitance and residual stress is hybrid integrated with the interface circuit using ic nude chip. so the density of the package is increased, and the noise of the sensing system is decreased. these found the base of capacitive accelerometer module using the mcm method

    該傳感器製作工藝簡單，靈敏度高，支撐梁採用u型，減小了刻蝕后的殘余應力，用玻璃作為襯底，減小了襯底和硅可動質量塊間的寄生電容，且把傳感器晶元和用ic裸片製作的介面電路集成在一起，提高了封裝密度，減小了傳感器系統的噪聲，為採用mcm技術製作電容式加速度傳感器模塊打下了基礎。
  10. The macromodel is built up with the combination of device simulation and nonlinear curve fit, which makes the extraction of the substrate parasitic parameters more convenient and the circuit simulation more accurate

    該宏模型通過器件模擬與非線性擬合相結合的方法建立，使襯底寄生參數的提取更加方便，同時保障了深亞微米電路特性的模擬精度。
  11. It also has short protection and voltage overshot protection block. devices and ics based on esoi have the advantages of not only cheaper substrate, good performance of soi technology, but also obtaining a certain breakdown voltage and optimization of self - heating effect

    基於esoi的器件及集成電路不僅襯底材料制備工藝簡單，硅層厚度均勻性好，器件及電路特性具有soi結構的優點，而且還兼顧一定的耐壓，對自加熱效應也得到優化。
  12. The demand of the wafer ' s quality become higher too. the result of the final polishing determines the quality of silicon substrate for the final polishing is the last step in the polishing. in this paper, the mechanism and dynamics process of silicon polishing are systematically analyzed

    隨著集成電路向著甚大規模集成電路（ ulsi ）日新月異的發展，作為襯底材料的硅單晶片的尺寸越來越大，特徵尺寸也不斷減小，對硅襯底拋光片的拋光質量的要求也越來越高。
  13. Up to present we have prepared the epitaxial simox substrate ( i layer 0. 37um, silicon layer 2. 8um ), and done the circuit design, process integration, device simulation and some layout design )

    本項目目前已完成了simox外延襯底的制備（ i層0 . 37um ，外延硅層2 . 8um ） ，以及功率開關集成電路的電路設計，工藝設計和部分版圖設計。
  14. Microelectronic circuits in which the passive components and their metallic interconnections are formed directly on an insulating substrate and the active semiconductor devices ( usually in wafer form ) are added subsequently

    一種微電子電路器件，其中的無源元件及內部金屬連線直接在絕緣襯底上形成，然後再加上有源半導體器件（通常以大圓片形式給出） 。
  15. Especially, mesfet devices fabricated on lec si - gaas substrate have been adopted into very large - scale integration ( vlsi ) and monolithic microwave integrated circuit ( mmic ) extensively. therefore, it is necessary to study the influence of defects in substrate material of lec si - gaas on performance of mesfet to meet the need of design and fabrication of gaas ic

    以液封直拉半絕緣gaas為襯底的金屬半導體場效應晶體管（ mesfet ）器件是超大規模集成電路和單片微波集成電路廣泛採用的器件結構，因此研究lec法生長si - gaas （ lecsi - gaas ）襯底材料特性對mesfet器件性能的影響，對gaas集成電路和相關器件的設計及製造是非常必要的。
  16. With the development and application of the microwave communication system 、 precision guided technologies and electronic countermeasure etc, the research on dielectric materials such as circuit dielectric substrate 、 antenna unit dielectric substrate and radome are paid more and more attention

    隨著毫米波通信系統、精確制導、電子對抗等技術的發展和應用，對電路介質基片、天線單元介質襯底、天線罩等介質材料的研究越來越受到重視。
  17. We have done the following work in this paper : 1. proposal of a novel high - voltage soi lateral structure ( tsoi ), and establishment of its blocking theory ; 2. proposal of devices based on epitaxial simox soi ( esoi ) substrate ; 3

    本文主要進行了三個方面的工作： 1 、提出了降場電極u形漂移區的橫向高壓器件結構tsoi （ trenchsoi ） ，並建立了該結構的解析理論[ 1 ] ； 2 、提出基於simox外延襯底esoi （ epitaxialsimoxsoi ）的器件結構； 3 、設計了基於simox處延襯底結構的功率開關集成電路。
  18. The degradation and lifetime model is deeply discussed, dynamic and static stress suffered by devices and circuits are compared and analyzed. a modified model for lc is proposed for better fitting the experimental data and the substrate current model parameters eerit and lc, degradation parameter h, m, n are extracted by the static stress experiment results

    詳細分析討論了mosfet的壽命與退化模型，並對電路中器件所受的動態應力與直流靜態電應力進行了分析比較：根據實驗結果改進了有效導電長度l _ c模型；應用直流電應力實驗數據進行了襯底電流模型中載流子速度飽和電子科技大學博士論文臨界電場e ； 、有效導電長度lc以及退化參數h 、 m和n的提取。
  19. A type of two layers pbg structure band stop filter with holes in the substrate is introduced in this paper, it detaches the substrate and microwave circuit, which solves the problem of placing microstrip line and helps to manufacture and amend, both the simulation result with hfss and measurement results are given out to identify its possibility

    摘要本文介紹了一種雙層結構的基於襯底打孔的pbg結構帶阻濾波器，採用了周期結構與微帶電路分離的設計，解決了傳統的打孔結構的導帶加工問題，並且有利於電路的加工和修改。
  20. The temperature sensing circuit adopts current - output mode taking pnp substrate transistor as temperature sensing device. according to the theory of the bgr, ptat and ctat can be generated from the circuit, and the former one is regarded as the initial signal which correlating to the temperature

    溫度傳感電路以襯底pnp型bjt作為感溫元件，採用電流輸出模式，按照帶隙基準原理獲得與絕對溫度成正比（ ptat ）電流以及與絕對溫度成反比（ ctat ）電流，並以前者作為與溫度相關的原始電信號。
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