電鐘同步器 的英文怎麼說

中文拼音 [diànzhōngtóngbùqì]
電鐘同步器 英文
electric clock synchronizer
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 步 : Ⅰ名詞1 （步度; 腳步） pace; step 2 （階段） stage; step 3 （地步; 境地） condition; situation; st...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  2. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  3. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  4. In this thesis, the principle of polarized light wave transmit in optical fiber is researched, i. e. principle of ternary optical fiber communication is researched. based on the researches, the construction of ternary codes optical end machine and 3b2t optical end machine used in two - state fiber net are designed. the construction and component of circuits in 3b2t optical ( called sign converter circuit - scc ) are designed particularly, including : the clock synchronization module, the data synchronizing, code converting module, frame managing module and error exam and managing module

    本文研究了線偏光波動理論以及在光纖中的傳輸原理，研究了三值光通信系統原理和器件原理；在此基礎上，設計了三值光端機和在現有兩值光纖網中實現三值光通信的3b2t三值光端機的組成結構，詳細設計了3b2t三值光端機的電路組成部分（稱為電信號變換電路scc ） ，包括：時鐘同步模塊、數據同步模塊、碼元變換模塊、幀處理模塊及差錯檢測和處理模塊；而且在三值光纖通信基礎上，提出了四值光通信的原理和偏分復用的實用化方法。
  5. After power switch opening, the clock displayer display asynchronous timing information, so synchronous indicating lamp glimmer, when equipment receiving above four effective satellite information and getting synchronous, which synchronous indicating lamp blank off

    電源開關打開后，時鐘顯示器顯示未同步的時間信息，同步指示燈閃爍，裝置接受到四顆以上的有效衛星信息，並取得同步后，則同步指示燈熄滅。
  6. To synchronize your pc clock with the hong kong observatory s network time server, please follow the steps below

    若要將你的電腦時鐘與天文臺的時間伺服器同步校對，請按照以下步驟進行:在
  7. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。
  8. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
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