高速串列介面 的英文怎麼說

中文拼音 [gāosùchuànlièjièmiàn]
高速串列介面 英文
h i high- eed serial interface
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 列 : Ⅰ動1 （排列） arrange; form a line; line up 2 （安排到某類事物之中） list; enter in a list Ⅱ名詞1...
  • 面 : Ⅰ名詞1 （頭的前部; 臉） face 2 （物體的表面） surface; top 3 （外露的一層或正面） outside; the ri...
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 介面 : joggle; nozzle; mouthpiece; [計算機] interface
  1. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  2. Thirdly, the system can transfer data to pc at a high speed on the series interface based on usb2. 0 technology, which is satisfied with the demand for a great many data transmission

    本系統運用usb2 . 0高速數據串列傳輸介面技術，實現了數據串列高速傳輸，滿足了高數據吞吐量要求。
  3. The tramsission rate exceed to the range of isa bus, moreovcr the pci bus can be competent for the rate request. the card makes use of the total line in pcicontroller, the slice of fifo, fpga and super - speed a data correspondence chip, which can solve the transmission stream and total line in pci connecting problem. and realizes the mpeg - 2 deliver to flow with establish outside delivers

    此速率超過了isa總線所能支持的傳送速率，而pci總線能夠勝任這一要求，由此確定節目傳輸流發送卡採用pci總線。此卡利用pci總線控制器、 fifo晶元、 fpga晶元、高速串列數據通信發送晶元，解決傳輸流與pci總線之間的介面問題，實現了mpeg - 2傳輸流與外設的高速數據傳輸。
  4. A design of high - speed serial digital interface

    高速數字串列介面的設計
  5. A novel receiver in high - speed serial data interface usb 2

    一種新型的用於高速串列介面電路中的接收器
  6. Hssi high - speed serial interface

    高速串列介面
  7. High speed serial interface

    高速串列介面
  8. High - speed serial interface for data terminal equipment and data circuit - terminating equipment

    數據終端設備和數據電路終接設備的高速串列介面
  9. The 80c196kc single chip microprocessor, electronic switch array, cpld, large capacity ram were integrated into the interface card. the detection operation is intelligent and automatic. the control software and the virtual instrument panel were designed in visual c + +, different messages were sent through serial port

    在檢測系統中設計了具有高速并行數據採集及處理功能的介面卡，介面卡上採用80c196kc單片機、電子開關陣列、大規模門陣列（ cpld ） 、大容量存儲器等器件，實現了智能化、自動化檢測；在微機軟體設計上，運用visualc + +語言編制了虛擬儀器面板程序和控製程序，通過微機串口向單片機發送各種信息。
  10. According to the electromagnetic induction theory, abrupt variation of current in the transmitter loop will induce magnetic field around it, which is called the first field. in the transmission of the first field, when it meets good conductor target, induce current will be created, which is called erratic current of second current. because the second current changes with time, so it will create new magnetic field, which is called

    對于接收部分，由於瞬變信號具有早期信號幅度大、衰減快，而中晚期信號幅度小、衰減慢的大動態范圍的特點，必須設計適應這種大動態范圍信號的採集電路;為了適應野外工作，系統主控部分採用具有功耗低、高速處理的dsp ，通過高速通用串列介面usb與上位機通訊，實現對整個探測系統的控制。
  11. The system abandons the serial communication that is low speed and low effect, but change to use the printing port, realizes the high speed, efficient parallel communication, further more choose to use to the ecp ( extended capabilities port, ) mode of parallel communication. according to the outside physical transfer ability, this mode can automatic adjust the transfer speed, and realize the data communication with the arbitrary speed

    該系統在上下位機的數據傳輸中，摒棄了低速、低效的串列通訊，而改用列印口，實現了高速、高效的并行通訊，並且選用了並口的ecp （ extendedcapabilitiesport ，擴展功能介面）模式，可以根據外設的實際傳輸能力自動調整傳輸速度，實現任意速度的數據通訊。
  12. The logical architecture, protocol, the encoder algorithm, the decoder algorithm and the electronics specification of the tmds which is the core of the dvi and means transition minimized differential signal are described in particular in this paper. and the synchronization and data recovering which mean the central problem in the high speed serial data communications are also analyzed

    本文以dvi介面通訊協議為主線，詳細介紹和分析了作為介面核心內容的tmds ? ?最小變化差分信號的邏輯架構、通訊協議的編碼演算法、解碼演算法、 tmds信號的電氣規范等問題，並著重分析了作為高速串列通訊的關鍵問題的鏈路時鐘同步與數據恢復問題。
  13. Microprocessor ' s i / 0 is the seria1 interface chip, making the system simplified and reliability increased. the state and seat of throttle. clutch and brake, the rotates speed of engine, the direction of motive force etc are the paraneters

    自動控制系統硬體電路以at89c52為核心，沒有外擴ram 、 rom ， i / o介面晶元採用串列工作方式，接線簡單，可靠性高；設置油門、離合器、剎車狀態和位置，發動機轉速，動力流向等傳感器獲取運行參數。
  14. The thesis is composed of 9 parts : the background, significance, main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2, the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7, a fixed equalizer for 2. 5gbps transceiver is described ; in chapter 8, layout design and measured results are discussed ; at last, the conclusions are drawn in chapter 9. during period of finishing the thesis, i read lots of literatures about the interface circuits in high - speed data transmission system, studied their principles and design techniques, and designed : 1 、 the line driver for 2. 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2. 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1. 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver

    論文由9部分組成：在第一章引言中介紹了論文的背景、意義、國內外研究現狀，以及論文的主要內容和創新；第二章以千兆位以太網為例，從系統的角度介紹了高速數據傳輸系統介面電路的主要功能和性能指標；第三章分析了高速數據傳輸系統的傳輸介質的頻率特性和模型；第四章描述了線驅動器的設計原理及其電路實現；第五章描述了高速數據傳輸系統的均衡原理；第六章描述了適用於1 . 25gbps基帶銅纜收發器系統的自適應均衡器的設計原理和電路實現；第七章描述了適用於2 . 5gbps基帶銅纜收發器系統和1 . 5gbps串列硬盤介面（ sata ）收發器系統的固定均衡器的設計原理及其電路實現；在第八章中分析了電路的版圖設計及晶元測試結果；最後，第九章總結了全文。在完成論文期間，查閱了大量的有關高速數據傳輸系統介面電路方面的文獻，較系統地學習了線驅動器、傳輸線和均衡器等方面的理論知識和電路設計原理，設計了用於： （ 1 ） 2 . 5gbps基帶銅纜收發器系統的線驅動器； （ 2 ） 2 . 5gbps基帶銅纜收發器系統的固定均衡器； （ 3 ） 1 . 5gbpssata系統的固定均衡器； （ 4 ） 1 . 25gbps基帶銅纜收發器系統的自適應均衡器。
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