高速緩存 的英文怎麼說

中文拼音 [gāosùhuǎncún]
高速緩存 英文
caching
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 緩存 : buffer
  1. He job of cache coherency is done partially by the hardware and partially by the operating system

    保證高速緩存一致性的工作由硬體和操作系統共同分擔。
  2. This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches

    本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。
  3. Their write cache whenever the system is rebooted or suspended

    它們的寫高速緩存。
  4. This would undoubtedly introduce further complexity, including the need for acknowledgement of messages and the queuing or caching of unacknowledged messages until the user returns online

    這無疑會引起更復雜的問題，包括對消息的認可以及排列或高速緩存不被認可的消息，直到用戶在線回答。
  5. The overhead of this request can make a system unscalable if the validating parser does not cache the schema definitions

    如果確認解析器沒有對模式定義進行高速緩存，這種請求的開銷會使系統失去可擴展性。
  6. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    性能的提高主要是由於三個方面的改進： 1 .處理器及高速緩存性能的優化2 .降低內存瓶頸：通過對powerplus體系結構的改進，使內存性能提高到582mb s memory read bandwidth和640mb s burst write bandwidth 3 .系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mb s ， powerplus ii則能達到80mb s而無須消耗額外的cpu資源。
  7. In the third chapter, the hardware design of the radar echo simulator is introduced, including the unitary chart of hardware structure and design of each part in this system, which is composed of designs of computer interface, controlling sdram and controlling ide harddisks and some introduction about d / a and fpgas used in this system

    再次，介紹了本雷達回波模擬器的硬體設計，包括總體硬體結構框圖、系統各部分的硬體設計。系統各部分的硬體設計包括計算機介面設計、大容量高速緩存sdram的控制設計、 ide介面硬盤的控制設計、關于d / a的介紹和本系統使用的fpga的介紹。
  8. It adopts genetic algorithm in schedule strategy to improve the quality of system data source, ( 2 ) the local store module to manage the web snapshot content of frequent words, this can reduce the system complexity, saves store space

    它使用基於遺傳演算法的調度策略提高系統數據源的質量。 （ 2 ）本地緩存模塊用來管理高頻查詢詞對應的網頁快照內容，以降低系統的復雜度和減少系統所需的存儲空間，同時使用高速緩存來提高檢索速度。
  9. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  10. For soap applications, we use dynamic proxy factory to realize the integration. this paper makes some contributions on bringing out the architecture that combines soap service and knowledge - based system, especially setting up criterions for dynamically registering wrappers that wrapper legacy application

    本文的創新之處在於，將知識系統與soap技術融合；通過wrapper機制實現動態注冊輕松實現系統集成；通過ldap高速緩存消息達到提高系統效率的目的。
  11. The high - speed data buffer is designed by adopting cpld and general high - speed static memory. 5

    採用cpld控制邏輯外加通用靜態高速存儲器來實現採集后數據的高速緩存。
  12. Install the dynamic cache monitor

    安裝動態高速緩存監控器。
  13. Next, the cache monitor must be mapped to a virtual host

    接下來，必須將高速緩存監控器映射到虛擬主機。
  14. Table 9. cache management instructions

    表9 .高速緩存管理指令
  15. The powerpc architecture contains cache management instructions for both application - level cache accesses

    Powerpc體系結構包含了面向應用級高速緩存訪問的高速緩存管理指令。
  16. This work is focused on the research of the real time response 、 transplantable 、 reducible and configurable of the file system

    Deltafile文件系統分為三個實現層次，分別是:虛擬文件系統、邏輯文件系統和塊高速緩存。
  17. The implementation of deltafile 3. 0 can be divided into two modules ? real - time file system module and manage module for both facilities and drives. the real - time file system contains four parts ? system call api layer, file node manage layer, virtual file system layer, concrete file system layer, which perform the abstraction of the facility

    實時文件系統模塊包含系統調用api層、文件節點管理層、虛擬文件系統層、具體邏輯文件系統層四部分，主要完成與設備無關的數據存取介面抽象和各種文件系統標準的實現;設備與驅動管理模塊包含邏輯設備管理層、物理設備管理層、設備緩沖區高速緩存層、設備驅動管理層四部分，主要完成外部存儲設備管理及其驅動介面抽象功能。
  18. Fast - 8 mb cache - keeps more of your data in high - speed memory for unsurpassed performance in its class

    - 8 mb高速緩存-把您更多的數據保存在高速存儲器中，使其在同類中具有無可比擬的性能。
  19. Aspects written in earlier phases of learning tend to focus on auxiliary concerns that can be unplugged from the system and on horizontal concerns that apply across many domains such as transaction management, caching, or tracing

    前期學習階段編寫的方面側重於可從系統拔出的輔助關注點和跨許多域應用的水平關注點（比如事務處理管理、高速緩存或跟蹤） 。
  20. There are five different types of advanced caching

    有五種不同類型的高級高速緩存：
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