點運算 的英文怎麼說

中文拼音 [diǎnyùnsuàn]
點運算 英文
point operation
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 運 : Ⅰ動詞1 （物體位置不斷變化） move; revolve 2 （搬運; 運輸） carry; transport 3 （運用） use; wield...
  • 算 : Ⅰ動詞1 （計算數目） calculate; reckon; compute; figure 2 （計算進去） include; count 3 （謀劃;計...
  • 運算 : [數學] operation; arithmetic; operating
  1. In general, the operation of insertion of removal of vertices of degree 2 does not affect the planarity of a graph.

    一般地，插入或移去2次頂點運算，並不影響一個圖的平面性。
  2. In the phase of image pretreatment, the main jobs of this system includes dot operation, image swell, positive chiasma transform, edge extraction and edge swell, outline track, etc. because the visual system itself is a neural system, systematizer designed in the paper adopts bp neural network to accomplish computer image identification, the system has some advantages over the traditional one, but with the extensive application of bp neural network, the problems existing in bp neural network come forth increasingly

    在系統軟體設計部分中，首先是對所選零件進行模式識別，包括圖像預處理、特徵提取和分類器設計三個階段，其中在圖像預處理階段本系統主要做的工作有：點運算、圖像增強、正交變換、邊緣提取和邊緣增強、輪廓跟蹤等。由於視覺系統本身就是一個神經系統，故本文所設計的分類器採用bp神經網路，其具有一些傳統技術所沒有的優點。
  3. As of the middle of 2001, the world s fastest computer can perform, on average, about five trillion floating point operations per second, or 5 teraflops. the machine that ranks 500th averages about 55 gigaflops

    在2001年中期，世界上最快的計算機可以平均每秒執行5萬億次浮點運算，也就是5 teraflop （ teraflop每秒1萬億次浮點運算） 。
  4. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  5. To access them, use the dot operator

    ；若要訪問這兩個成員，請使用點運算符：
  6. For example, the dot operator is used to access the property named

    中，使用點運算符來訪問
  7. The dot operator specifies a member of a type or namespace

    點運算符指定類型或命名空間的成員。
  8. The dot operator is typically used for accessing the properties of an object

    點運算符通常用於訪問對象的特性。
  9. Furthermore, the dot operator and the bracket operator are interoperable

    此外，點運算符和方括號運算符還可以互操作。
  10. As was true of the dot operator, the bracket operator can be applied recursively

    和點運算符一樣，方括號運算符也可以遞歸應用。
  11. The dot operator

    點運算符（
  12. Finally, the dot operator and the bracket operator are somewhat interchangeable

    最後，點運算符和方括號運算符可能實現某種程度的互換。
  13. Fpu float point unit

    浮點運算單元
  14. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  15. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  16. Binary floating - point arithmetic for microprocessor systmes

    微處理器系統的二進制浮點運算
  17. Binary floating - point arithmetic for microprocessor systems

    微處理機系統的二進制浮點運算
  18. Radix - independent floating - point arithmetic

    與基數無關的浮點運算
  19. Then floating - point arithmetic is performed

    ，則執行浮點運算。
  20. Binary floating - point arithmetic

    二進制浮點運算
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