adsp 中文意思是什麼

adsp 解釋
無水磷酸氫二鈉
  1. 3. design and debug mti / mtd program of one piece of adsp - ts203

    3 .在另一片ts203中完成了動目標檢測和顯示單元的程序設計和調試。
  2. Adsp sharc21060 is one of current digital signal processing boards based on super harvard architecture, and it " s architecture is designed to streamy parallel

    Adspsharc21060是一種基於超級哈佛結構的通用數字信號處理器， sharc的結構被設計為流水線并行處理器。
  3. High speed multi - channel data recorder based on adsp - ts

    201的高速多通道數據記錄儀
  4. 2. design the pulse compression program of one piece of adsp - ts203. complete the program and optimization of radix - 2 fft independently, which meets real - time processing

    2 .基於一片ts203的脈沖壓縮處理單元的程序設計，獨立完成其中基2 - fft的編寫及其優化，滿足系統實時性的要求。
  5. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  6. Considering the developmental trend of the video compress and the demands of the people, this paper makes researches on the visual section of the mpeg - 4 standard, present an amendment to the ds search algorithm, and does some optimization to the module of compress which is utilized frequently by the encoder so that the encoder can accomplish real - time compression on adsp - blackfin535 evm board to the cif picture, the size of which is 352 by 288

    因此，研究mpeg - 4視頻編碼標準並實現實時編解碼具有重要意義，特別是在圖像質量和實時性方面要求都很高的場合，例如電視會議、視頻電話和iptv等。本文結合這種需求和趨勢，研究了mpeg - 4sp編碼原理，改進了ds演算法。通過內存優化、結構優化和匯編級優化，最終實現了編碼器在adsp - blackfin535評估板上的實時編碼。
  7. In this paper, after the theory of video coding analyzed and some video compression standard compared, the development, constitution, application and characteristic of h. 264 video compression technique is focused on. and then the design of h. 264 video capturing and coding system based on adi dsp ( adsp - bf561 ) is illustrated, the hardware constitution and the software realization of the real - time video encoder are introduced particularly, and all kinds of techniques to optimize the h. 264 program according to the hardware configuration and compiling characteristics of adsp - bf561 are discussed especially

    本文在分析了視頻編碼的基本原理，並將目前常用的視頻壓縮標準進行了比較的基礎上，重點分析了h . 264視頻壓縮技術的發展、組成、應用及其特點，詳細論述了以adidsp （ adsp - bf561 ）為核心的h . 264視頻採集編碼系統的硬體組成和軟體實現，著重闡述了根據adsp - bf561系統的硬體及編譯系統特點，運用各種方法對h . 264編碼程序代碼進行優化的方法，最終實現了基於adiadsp - bf561的h . 264視頻採集編碼。
  8. In this paper, real time torpedo homing system. which is based on adsp ? 2106x to be discussed. high speed signal parallel processor system is researched, it is made up of intel 80c186eb processor main board and adsp _ 2106x. it can be come true using this system for the accuracy parameter estimation of underwater target which moves on high velocity

    本課題是以高速并行數字信號處理晶元adsp ? 2106x為核心，以intel80c186eb微處理器構成的cpu模塊為主控板，構成完整的高速并行數字信號處理機硬體系統，該硬體系統可以成功地實現現代魚雷自導的水下高速運動目標參量實時精估演算法。
  9. Three algorithms for pseudo - random fsk / psk radar signals ’ sidelobe suppression such as spectrum modifying, direct mismatch filters and neural network. 3. using adsp 21160 to design dsp programs with assembly and c languages for the three algorithms mentioned above on visualdsp + + 3. 5 integrated development environment

    3 .用adi公司的sharc系列晶元adsp21160 ，在visualdsp + + 3 . 5集成開發軟體平臺上，完成以上三種旁瓣壓縮演算法實現的匯編、 c語言程序設計和調試工作。
  10. Lastly, this paper discussed the realization of the three sidelobe algorithms mentioned above using adsp 21160 which is a product of adi sharc serial digital signal processor

    最後，採用adi公司sharc系列dsp晶元adsp21160n探討了偽隨機fsk / psk信號旁瓣抑制演算法的dsp實現。
  11. In the first part of this paper, different kinds of usual network architecture of parallel - processing multi - processors are studied. based on adsp - 21160 serial digital signal processors from ad company, close - coupled flexible hardware network architecture is selected as the network architecture of the system, because of which the hardware logical architecture of the system can be recomposed on line according to the acquirement of different algorithms

    本文第一部分研究了各種常見的并行處理網路結構，基於ad公司的adsp - 21160系列數字信號處理晶元，選擇緊耦合的柔性硬體結構作為該系統的并行處理結構，使得系統的硬體邏輯結構可以根據演算法的要求在線重組。
  12. In our paper, we firstly summarize the development of low rate video communication, before we implement h. 263 encoder to the adi ( analog devices incorporated ) evaluation board - - - - - adsp - bf535 ez - kit lite ; we make in - depth research about h. 263

    本文首先概述了低碼率視頻通信的發展，然後對低比特率的視頻編碼標準h . 263進行了深入的研究;並在adi （ analogdevicesincorporated ）公司的adsp - bf535ez - kitlite評估板上的實現了h . 263視頻編解碼器。
  13. The main works were listed below : 1. as the core of image tracker, the advanced dsp technology ( adsp - ts201 ) and the programmable logic device ( ep1s40f1020 chip ) were combined together to make certain that instruction was completed within single instruction period

    主要體現在下面幾點: 1 .圖像跟蹤器的硬體平臺以先進的dsp技術（ adsp - ts201 ）和可編程邏輯器件（ stratix系列的ep1s40f1020晶元）為核心，構成實時的圖像跟蹤處理器，使得指令可在單指令周期內完成運算。
  14. It is based on the mean square error ( mse ) principle and we prove the validity of the method by computer simulations. to make a thorough understanding of mimo adaptive equalization system, in this thesis the author : 1 ) ananlyze the characteristics of mimo wideband channels and the modeling and simulation of 3gpp scm ; 2 ) research the capability of mimo linear adaptive equalization and mimo non - linear adaptive equalization by computer simulations ; 3 ) present a new method for selecting the order of adfe model 4 ) implement the adfe on adsp - 21160 for static image transmission, and already achieve satisfactory experimental result, which make a foundation for mimo adaptive equalization to be appllied in the real communication systems

    為對mimo自適應均衡系統性能和設計做更深入的理解和研究，本文主要: 1 ）研究了寬帶選擇衰落通道特性及3gppscm通道建模模擬; 2 ） mimo線性自適應均衡器和mimo非線性自適應均衡器系統的性能分析和模擬實現; 3 ） mimo系統下的判決反饋均衡器的階數選擇模擬試驗分析; 4 ）把mimo自適應判決反饋均衡運用到了硬體模擬平臺上，採用了基於adsp - 21160的硬體dsp開發板，對靜止圖片的傳輸進行了試驗、分析和比較，得到了較滿意的實驗結果，使mimo自適應均衡在實際通信系統上的應用及實現奠定了現實基礎。
  15. This thesis deals with design and application of a multiprocessor made of four dsps in monitoring receiver. the broadband monitoring receiver requires a kind of chip with high performance because of complicated intermediate frequency signal processing. the author selects a kind of digital signal processor called adsp21160. during the process of design, the author uses cpld, fpga and some special cpus to finish signal, processing in the monitoring receiver. cluster multiprocessor based on vxibus made of four adsp21160 is put forward. the task distribution of four dsps is solved too. furthermore, data transition methods between chips at a high speed through link ports and chip extension mode using external port are recommended. the author debugs, emulates the program in one adsp - 21160 ez - kit lite and simulates the multiprocessor program in visualdsp + +

    本文主要探討了監測接收機中多dsp處理模塊的設計與應用，寬帶監測接收機的中頻處理數據量大、實時性高，這樣，對dsp晶元提出了很高的要求，作者通過比較選擇了最適用於監測接收機的數字信號處理器adsp21160 ，並結合使用了cpld 、 fpga以及一些專用的cpu來完成監測接收機中的數據處理。作者提出了由四片adsp21160組成的簇式多dsp處理模塊的結構並配以了vxi總線，論述了簇式結構的特點，解決了多dsp處理模塊中四片adsp21160的任務分配問題。
  16. With phased array radar observing target ' s improvement of different performances of the aircraft, the deterioration of the working environment of radar and improvement of the radar demand request more and higher for putting forward the equipment of phased array radar video signal processing. the digital signal processing is all the time the developing direction of radar signal processing, its main shortcoming is that the increase processing precision, and the amount of information at the same time bring on the amount processing redouble, method to solve this problem is the real - time high speed digital signal processing system. presently multi - processors parallel processing is the focus of the field of high - speed real - time processing. this paper ' s background is the high - speed real - time signal processing of phased array radar. a parallel computing system designed with 4 adsp - 21060 analog device inc ' s dsp is presented. lt has fully utilized the dsp ' s characteristic to be supported the parallel computing, and formed a mes h architecture. this paper design and discusses this system in terms of design for test ( dft ) and real time operation system ( rtos ), and have put forward the new solution for the design and development of the high - speed real - time signal processing system. then, analysed the subject matter faced at the same time

    本文以高速實時相控陣雷達視頻信號處理為背景，提出了一種由4片ad公司adsp - 21060構成的并行計算系統。它充分利用了adsp - 21060支持多處理器并行計算的特點構成了一種網格結構，並且從可測性設計、實時操作系統角度對該系統進行了設計與討論，為高速實時信號處理系統的設計與開發提出了新的解決方案，同時分析了面臨的主要問題。本文首先分析了相控陣雷達信號處理單元的特點，然後針對適合於片間并行的adsp - 21060討論了并行計算結構，提出了一種採用四片adsp - 21060構成網格結構的信號處理平臺，分析了它的工作原理。
  17. Based on the familiarity with compiling environment and work theory of u - boot, and combine with the character of adsp bf561 processor, we transplanted the u - boot. and then we transplanted uclinux by adding and amending relative files for adsp bf561 ez - kit lite board after analyzing the process of uclinux startup. in order to enable the processor adsp bf561 to be competent for some complex task, we must develop drivers for the periphery devices

    本文在熟悉u - boot的編譯環境和工作原理的基礎上，結合adspbf561的特性，首先為adspbf561ez - kitliteboard移植了u - boot ，然後研究了uclinux的文件組織體系結構以及uclinux的啟動流程，根據uclinux的啟動流程修改和添加相應的文件從而把uclinux移植到adspbf561ez - kitliteboard上。
  18. This dissertation mainly studies the radar digital pulse compression processing in frequency domain, mobile target indication ( mti ) and mobile target detection ( mtd ) system based on two pieces of adsp - ts203

    本文主要研究基於兩片adsp - ts203的雷達頻域數字脈沖壓縮和動目標顯示及動目標檢測（ mti / mtd ）系統。
  19. In this dissertation the pulse compression performances of linear frequency modulation signals ( lfm ) and the algorithm of mti / mtd are analyzed. programme and its optimization of them based on 2 pieces of adsp - ts203 are introduced in detail

    全文主要分析了線性調頻信號（ lfm ）的頻域脈沖壓縮方法及mti / mtd的演算法;詳細介紹了基於兩片ts203的脈沖壓縮和mti / mtd的程序設計及其優化。
  20. The purpose of this dissertation is to transplant uclinux for adsp bf561 ez - kit lite board

    本文的設計目的是為adspbf561ez - kitliteboard實現嵌入式uclinux的系統移植。
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