altera 中文意思是什麼
altera
解釋
阿爾特拉-
In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software
在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。 -
At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language, and its ip core is also achieved which is used not only in the satellite navigation position system, but also in the long pn code dsss system. ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project, and the technology has the definite theory and practice significance
此外還應用altera公司的最新的fpga開發工具quartusiiv5 . 1 ，採用了國際標準的硬體描述語言? vhdl語言，對數字差動匹配濾波器和傳統匹配濾波器演算法予以實現，開發了該演算法的軟ip核，可以對所應用的擴頻碼長度， a / d采樣后的數據量化階數，所用擴頻碼等可進行隨意改寫。 -
Cryptogrammic chip introduced in this paper has been tested on the altera ' s apex20ke fpga. the main clock frequency reached 40mhz. the chip includes 30, 000 les. in order to utilize esb resource in altera ' s chip, we adopted embedded rom and ram and can realize the function of whole system with only one chip. lt is the embodiment of methodology and notion of sopc ( system on a programmable chip ). the simulation of this cryptogrammic chip proves the correctness of function of the chip, which shows that the important ideology based reconfigurable architecture has special significance in designing of cryptogrammic chip
本文所闡述的密碼晶元在altera公司的apex20kefpga上進行了測試。工作頻率達到了40mhz ，佔用了3萬個le . ，利用altera器件的esb資源，採用內置ram和內置rom設計方法，用一片晶元即可實現整個系統的功能，充分體現了sopc的設計方法和理念，對晶元的模擬和測試均證明晶元功能正確，表明基於可重組體系結構這一重要思想在密碼晶元設計中具有特殊的意義。該晶元的設計遵循hdl設計方法學的一般方法。 -
The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。 -
The encoder and decoders in the paper has been tested on the circuit board using the altera ’ s fpga of stratix gx ep1sgx25df672c7 with the system clock of 125mhz
本文的編解碼器採用altera公司的fpga晶元stratixgxep1sgx25df672c7在系統時鐘125mhz的情況下完成了電路板測試。 -
Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co. and the detailed analyses of typical examples are also given
結合altera公司classicep610晶元的結構，研究了將演化演算法應用於函數級數字組合邏輯電路的硬體演化，並且對典型實例進行了詳細分析。 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
This paper introduces the general design method of soc ( system on a chip ) using eda tools, gives some cases of ip, then implement a real system on epm7128slc84 - 15, a chip of altera company, this system including : scan and recognition of matrix keyboard, calculation of add, sutu multiply under the control of state machine, the display of result on computer screen
本文首先介紹了用eda工具設計片上系統的一般方法，給出了幾個ip ，然後在altera公司的晶元epm7128slc84 - 15上實現了一個soc實例，該實例包括：對矩陣式鍵盤的掃描、識別，在狀態機控制下進行加、減、乘法運算，以及結果在計算機屏幕的顯示。 -
The programmable logic device is programmed and simulated vvith max + plus ii of altera corporation, and the program is down loaded to the device through byteblaster parallel port dovvnload cable
可編程邏輯器件由altera公司的max + plus編程並模擬，由所製作的並口傳輸電纜線下載到硬體。 -
The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool, which has proved the feasibility and correctness of the circuit
採用硬體描述語言vetilog編寫了硬體電路程序，並使用synplicity的綜合工具synplifypro和altera開發工具quartus對電路系統進行了綜合與模擬驗證，證明了硬體電路的可行性與正確性。 -
A study of the methods of configuring altera fpga devices
器件的配置模式及其實現方法 -
This system is based on two altera ’ s statixii series fpga chips ep2s180f1020c5, and the tunner dtt7579 and the chip ad9433, together composed the main hardware platform. the hardware description system running on the fpga is the core of digital down converted sysgtem, synchronization system, estimation and equalization of channel system, 3780 - point fft ofdm demodulation system, frequency equalization system and ldpc decoding
以兩片altera公司的stratixii系列ep2s180f1020c5級聯為基礎構建了系統主硬體處理平臺，結合湯姆遜公司的調諧器dtt7579以及ad9433組成了系統的硬體構架fpga可描述硬體系統的核心任務包括數字下變頻，同步和通道均衡與估計， 3780點fftofdm解調，頻域均衡， ldpc解碼。 -
The accomplished design of iir filter is configured into chip and is tested in experimental circuit after configured. using altera ' s powerful developing software maxplus ii ， design entry ， design processing and design verification are carried out for all functional modules ， and so the whole design is accomplished
設計中選用了altera公司功能強大的maxplusii作為開發工具，在這個完全集成化的開發環境中，進行了各個層次的所有功能模塊的設計輸入、設計處理和校驗，完成了iir濾波器的硬體設計。 -
It is the first time that driving chip used by pdp is applied to the fed panel. by adopting the new ic and the novel driving method, the developed grey scale modulator achieve high flexbility, stability and high integration. the circuit system includes cyclonetm fpga from altera and stv7610 from st microelectronic. with the capability of generating two kinds of modulating waveform, it has the advantages of flexible configuration, high display - quality, high integration and low cost. fpga design is based on the quartus platform. data transforming and the system controlling are achieved by using single fpga
基於altera公司cyclone系列fpga和st公司stv7610驅動晶元設計的fed顯示器的灰度調制電路系統可以支持兩種調制波形，具有配置靈活，顯示性能好等優點，其集成度為原有系統的三倍，且造價更低廉;基於quartusii軟體平臺進行了fpga的系統開發與優化，採用單片fpga完成了全部的數據轉換和系統控制功能， fpga的可編程特性使系統的設計具有充分的靈活性和可擴展性。 -
This jpeg coding system is designed and simulated by quantursii software which is the fpga design tool of altera company. hole design need nearly 12600 lcs of cyclone device
本設計採用altera公司的quartus軟體設計和模擬，採用cyclone系列器件需要約12600個lc 。 -
The ep2s15 of altera company, work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller
Altera公司的ep2s15作為系統的外圍控制器，實現對系統的fifo （先進先出存儲器）與采樣時鐘的控制。 -
What we have adopted in this system are the digital tuner dtq - 1a of philip tda10046, and the fpga of acex series produced by altera corporation, and the idt7206 fifo produced by idt corporation. the staff of the project also completed the communication - controlling program and wince drivers for this card, along with the application program dedicated for the system. the system can carry out the following tasks : receiving, demodulation, decoding, and playing back of the terrestrial - broadcasting data
接收板採用基於philip公司的tda10046的dtq - 1a數字調諧器、 altera公司的acex系列ep1k30qc208以及idt公司的idt7206的先進先出存儲器（ fifo ） ，輔以自己編寫的通信控製程序，以及基於wince驅動程序開發和上層應用程序開發，實現了數字地面電視廣播的接收、解調、解碼、及播放等一系列功能。 -
The chip used here is epf10k10lc84 - 4 of flex 10k made in altera
最後，用fpga對系統進行功能驗證。 -
2. make download cable by principle of altera corporation ; 3
製作下載電纜，根據altera公司提供的原理圖； 3 -
The ep1k10tc100 which is belong to altera ' s acex 1k series is selected to be configured
設計中選用的高密度可編程邏輯器件是altera的acex1k系列的ep1k10tc100 。
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