arithmetic unit 中文意思是什麼

arithmetic unit 解釋
計算單位
  • arithmetic : n. 1. 算術，演算法；計算。2. 算術書。
  • unit : n 1 個體，一個，一人。2 （計值、組織、機構）單位；單元；小組，分部；【軍事】部隊；分隊。3 【機械...
  1. 2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path

    我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。
  2. Alu arithmetic - logic unit

    算術邏輯單元
  3. Arithmetic is divided into some basic units, such as analog input unit, digital input unit, calculated unit etc. a series of unit were connected by the input and output relation between them

    本文將監控過程中的演算法分解為通過輸入輸出介面進行連接的獨立環節，並將環節組合抽象為有向無環圖。
  4. According to the project of adaptive multi - rate speech coding ( amr ) being put forward by the third generation group of the mobile communication, this paper takes the principle of the speech arithmetic as the base, studies the technologies including the source controlled rate, voice activity detector, comfort noise and the error concealment unit in amr, discusses its the characteristic of adaptation and analyses its performances particularly. amr c codes are researched carefully through the modules being divided into and debugged under the tms320c54x provided by the ti corporation, and optimized in selecting the method of c code embedded assembler codes and simplified in the search codebook combining with the theory of speech coding, which are based on the realization about theory and practice of the optimization of amr speech coding

    從自適應多碼率語音編碼演算法的c代碼出發，對它進行模塊劃分後作了系統分析，將其在vc下調試通過，進一步在ti公司提供的tms320c54x環境中進行調試，結合語音編碼理論，對演算法進行優化，採用了在c代碼中嵌入匯編和簡化自適應碼本和固定碼本搜索的方法，部分地提高了c代碼效率，為實現自適應多碼率語音編碼的優化奠定了理論和實踐基礎。
  5. Usually point a kind of inside to pack the arithmetic figure cent the network with the box of the power enlarger. arithmetic figure type the power enlarger for method for signal for inputting for arithmetic figure comparing, at with arithmetic figure signal handling again and again partitioning the empress, then and respectively these signals transformation is imitating the signal, then again from eachly from of box enlarge the empress to go to again to push the the cowgirl in the box to pronounce the unit

    通常指一種內裝數字分頻網路和功率放大器的音箱。數字式音箱輸入的信號為數字比特流，在用數字信號處理的方法將音頻頻譜分割后，便分別將這些信號變換為模擬信號，然後再由各自的功率放大器放大后再去推動音箱中的相應發音單元。
  6. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  7. 3 - d graphics on mobile phones is quite similar to 3 - d graphics on pc in years past. there is no hardware acceleration, and processor speeds are quite low, and there also is the lack of floating point arithmetic unit in mobile phones

    因此論文從通用的部分開始論述，然後明了移動平臺的特徵，並試圖解釋三維引擎的一般原理和設計一個具有粗適性的基於游戲的三維圖形引擎。
  8. Each unit is extracted from the circuit, and is analyzed detailedly in framework, configuration and design approach. the instruction system of c9821 is unscrambled and then the instruction decode algorithm are obtained. the complete program of c9821 including basic arithmetic and root square operation is realized

    在軟體方面，破譯了c9821的指令系統，分析了指令譯碼電路的設計技術，分析了計算器內bcd碼的四則運算及開方運算演算法，得到了實現c9821全部功能的程序，掌握了該計算器的程序設計方法。
  9. Arithmetic control unit

    運算控制部件
  10. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  11. Arithmetic logic unit

    算術邏輯運算單元
  12. An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word - length restoration unit

    一種低功率消耗的算術裝置，其利用輸入主級閂、動態?圍偵測單元、控制轉換仆級閂、運算單元、位元數還原單元以構成。
  13. The part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register

    執行過程中的一個階段所需的時間，在此期間，計算機從主存儲器中取出指令或操作數，並將其存入控制器或運算器的寄存器中。
  14. Valu vector arithmetic logic unit

    向量算術邏輯單元
  15. Arithmetic logic unit data flow

    算術邏輯單元資料流
  16. Valu ector arithmetic logic unit

    向量算術邏輯單元
  17. Arithmetic and logic unit alu

    運算邏輯單元
  18. The arithmetic logic unit ( alu ), which performs arithmetic and logical operations

    算術邏輯單元，用來進行算術邏輯運算。
  19. Maximum time difference pipelined arithmetic unit based on cmos gate array. j. computer science and technology, 10 ( 2 ), 1995, ( with z. tang )

    大規模并行處理系統的反圖互連網路。香港?北京國際計算機會議論文集，北京， 1997 ， （與韓承德等合作） ， （特邀報告） 。
  20. A maximum time difference pipelined arithmetic unit based on cmos gate array. j. computer science and technology, 10 ( 2 ), 1995, ( with z. tang )

    大規模并行處理系統的反圖互連網路。香港?北京國際計算機會議論文集，北京， 1997 ， （與韓承德等合作） ， （特邀報告） 。
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