atpg 中文意思是什麼
atpg
解釋
測試圖形自動發生器-
The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究內容正是面向非掃描同步時序電路的并行atpg演算法。 -
In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future
第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga -
Also show that this algorithm excels previous iddt atpg algorithm
除了上面這些理論工作之外，結合實際應用，對排序演算法進行了研究。 -
Test is an indispensable task of vlsi circuits design. with the increased complexity of vlsi circuits, time overhead of atpg has become a bottleneck of design
隨著vlsi電路復雜性的增長，自動測試生成（ atpg ， automatictestpatterngeneration ）的時間開銷已經成為vlsi電路設計的瓶頸之一。 -
Finally, we analyse the performance of loosely coupled mode parallel atpg algorithms
國防科學技術大學研究生院學位論文最後，我們對松耦合模式的并行atpg演算法進行了性能分析。 -
In this thesis, we adopt loosely coupled mode, develop a series of effective parallel atpg algorithms based on sequential g - f two - value tg algorithm and hope fs algorithm
本文基於松耦合模式，以g - f二值tg演算法和hopefs演算法為基礎，快速開發了一系列有效的并行atpg演算法，獲得了良好效果。 -
The analyses reveal that, compared with traditional tightly coupled mode parallel atpg algorithms, loosely coupled mode parallel atpg algorithms can reduce time and memory overhead in theory
分析表明，和傳統的緊耦合模式的并行atpg演算法相比，松耦合模式的并行atpg演算法能夠減少時間和存儲開銷。 -
Etbi can conveniently and efficiently access the structure and function information of rtl circuits for atpg. this dissertation presents a format - transformer, which can transform iscas - 85 and iscas - 89 benchmarks verilog hdl descriptions to inner data structure, etbl, applied in rtl atpg
並且實現了相應的格式轉換器，將veriloghdl描述的iscas - 85和iscas - 89系列的rtl電路轉換為etbl描述的能運用於rtl電路測試產生的內部數據結構。 -
The automatic test vector generation method based on fault simulation is described, and the whole procedure of atpg of sequential circuits is analyzed, fault simulator - hope as an example
本文闡述了基於模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。 -
Since high performance control logics are usually hard for non - scan test generation, dft structures could be embedded as offsets in tradition, while it will cause manufacturing cost increase and performance overhead. in this paper, an indirect test generation method based on retiming is proposed, which could dramatically reduce the cost of non - scan atpg without any loss of original optimized attributes. experiments on some iscas 89 benchmarks show the benefits of our approach in enhancing atpg of performance - driven logic
對性能驅動控制邏輯進行測試生成難度較大，通常要加入可測性結構，但會影響原電路優化性能並增加生產成本.本文以重定時理論為基礎，提出了對高性能時序電路進行間接測試生成的方法，這種方法在不影響原電路任何優化特性的前提下，可顯著降低測試生成時間，提高測試生成質量.在iscas 』 89部分基準電路進行實驗，結果證明了其有效性 -
An automatic test pattern generation ( atpg ) algorithm for deliberately selected delay faults is presented to cope with the crosstalk - induced delay effects on longer paths
由於電路中較長的通路具有較短的鬆弛時間，因此容易因為串擾問題產生時延故障。 -
All the theoretical work is applied to 1c design and test applications with some examples. iddt atpg of genetic algorithm based on boolean process
作為布爾過程論的一個應用，針對動態電流測試，提出了動態電流測試的遺傳演算法測試方法。 -
This dissertation focuses on automatic test generation ( atpg ) algorithms for very large - scale integrated circuits at register - transfer - level ( rtl )
本文主要是對大規模、超大規模集成電路寄存器傳輸級（ rtl ）的自動測試產生演算法進行研究。 -
Based on rtl circuits structure described in etbl, this dissertation presents two hierarchical atpg algorithms based on structure for rtl combinational circuits. the two algorithms generate tests for rtl circuits by test sets for modules
本文在etbl描述的rtl電路結構的基礎上，進行rtl組合電路自動測試產生演算法的研究，提出了兩個基於結構的rtl組合電路分層測試產生演算法。 -
At present, the portability of atpg algorithm is the key of blocking its commercialization
目前，制約并行atpg演算法實用化的關鍵原因是演算法的可移植性。 -
This dissertation designs a data structure, etbl, for rtl circuits for vlsi atpg
本文根據超大規模集成電路自動測試產生要求，設計了rtl電路的數據結構etbl 。
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