baseband equalizer 中文意思是什麼

And i finished the layout design, chip test of line driver and equalizer in 2. 5gbps baseband copper cable transceiver and equalizer in the 1. 5gbps sata transceiver respectively. the main improvements and innovations in this thesis are as follows : 1 、 to design an analog equalizer tuned on - chip for 2. 5gbps baseband copper cable transceiver ; 2 、 to present an adaptive equalizer for 1000base - cx transceiver ; 3 、 to present an auto - gain control amplifier used in the adaptive equalizer for the 1000base - cx transceiver ; 4 、 to present an adaptive continuous - time gm - c filter in very high frequency for the adaptive equalizer for the 1000base - cx transceiver

論文主要的改進和創新有： 1 、設計了適用於2 . 5gbps基帶銅纜收發器系統片上可調的模擬均衡器電路； 2 、提出了一種新的適用於千兆以太網基帶銅纜收發器系統的自適應均衡器結構； 3 、設計了甚高頻自動增益控制放大器； 4 、設計了一種適用於千兆以太網基帶銅纜接收器均衡的自適應甚高頻連續時間gm - c二階帶通濾波器。

And it turns out that the bit error rate of passband equalizer is smaller than that of baseband equalizer, but the convergent stability of baseband equalizer is better than that of passband equalizer. at the same time, baseband equalizer can be implemented in hardware more easily than passband equalizer

通帶均衡系統的誤碼率總是小於基帶均衡系統的誤碼率;但基帶均衡器收斂后的穩定性要比通帶均衡器好，且基帶均衡器的采樣頻率較低，易於硬體實現。

The thesis is composed of 9 parts : the background, significance, main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2, the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7, a fixed equalizer for 2. 5gbps transceiver is described ; in chapter 8, layout design and measured results are discussed ; at last, the conclusions are drawn in chapter 9. during period of finishing the thesis, i read lots of literatures about the interface circuits in high - speed data transmission system, studied their principles and design techniques, and designed : 1 、 the line driver for 2. 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2. 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1. 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver

論文由9部分組成：在第一章引言中介紹了論文的背景、意義、國內外研究現狀，以及論文的主要內容和創新；第二章以千兆位以太網為例，從系統的角度介紹了高速數據傳輸系統介面電路的主要功能和性能指標；第三章分析了高速數據傳輸系統的傳輸介質的頻率特性和模型；第四章描述了線驅動器的設計原理及其電路實現；第五章描述了高速數據傳輸系統的均衡原理；第六章描述了適用於1 . 25gbps基帶銅纜收發器系統的自適應均衡器的設計原理和電路實現；第七章描述了適用於2 . 5gbps基帶銅纜收發器系統和1 . 5gbps串列硬盤介面（ sata ）收發器系統的固定均衡器的設計原理及其電路實現；在第八章中分析了電路的版圖設計及晶元測試結果；最後，第九章總結了全文。在完成論文期間，查閱了大量的有關高速數據傳輸系統介面電路方面的文獻，較系統地學習了線驅動器、傳輸線和均衡器等方面的理論知識和電路設計原理，設計了用於： （ 1 ） 2 . 5gbps基帶銅纜收發器系統的線驅動器； （ 2 ） 2 . 5gbps基帶銅纜收發器系統的固定均衡器； （ 3 ） 1 . 5gbpssata系統的固定均衡器； （ 4 ） 1 . 25gbps基帶銅纜收發器系統的自適應均衡器。