bist 中文意思是什麼

bist 解釋
阿拉伯學者
  1. The pseudorandom test pattern generation for bist

    基於內建自測試的偽隨機測試向量生成方法
  2. Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ), boundary scan and internal scan

    Jx5微處理器的測試結構由bist 、邊界掃描和內部掃描三部分組成。
  3. Since the chip has interior sram and it ' s difficult and slow to test sram exteriorly, in chapter four we use the technique of bist in design of testability of sram, which makes it possible to test the memory at normal working speed

    由於片內有sram ，而sram的片外測試比較困難且速度較慢，所以文中第四章採用bist技術對sram進行了可測性設計，完成後可以用正常的工作速度對存儲器進行測試。
  4. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  5. 3 zorian y. a distributed bist control scheme for complex vlsi devices. in proc. ieee vlsi test symposium vts 93, atlantic city, nj, 1993, pp. 4 - 9

    在混合bist方案中，我們會在偽隨機測試過程中終止偽隨機測試，因為剩下的偽隨機測試會降低偽隨機測試的故障覆蓋率。
  6. Bist is an efficient solution for the testing of soc. it is built up with prompting and responding circuits and these two parts are added to the circuit being tested so that the engineer need not consider the testing vector, for it ' s generated automatically

    而內嵌自測試技術對于解決soc生產測試的問題非常有效，它將一個激勵電路和響應電路中加到被測電路中，從而使測試人員不必再考慮測試向量的問題，因為它是自動生成的。
  7. In this paper we use the bist in the testing of the ssrams in estarl according to the characteristics of the structure and get almost 100 % fault coverage

    本文針對estar1內部ssram的結構特點，實現了存儲器自測試，得到了將近100的故障覆蓋率。
  8. It discusses the architecture of testbench in functional verification of dtv chip and detailed accounts realization of memory bist ( build in self test ) method

    本章介紹了各種主流驗證測試方法，著重敘述了dtv晶元中功能驗證的平臺結構設計和存儲器內建式自測試（ bist ）的具體實現。
  9. 6 sugihara m, date h, yasuura h. analysis and minimization of test time in a combined bist and external test approach. in proc

    換句話說，一個更長的偽隨機向量將會導致更長的測試時間，而與此同時會減少存儲確定型向量的存儲空間。
  10. Built - in self - test of logic blocks in fpgas finally, a free lunch : bist without overhead !. in proc. vlsi test symp.,

    對於一個具有4輸入lut的fpga來說，這與lut測試需要8次配置形成了鮮明的對比。
  11. Was soll denn die scheisse ? bist du denn verrueckt geworden

    你他媽在幹什麼?你怎麼搞的
  12. Test time minimization for hybrid bist of core - based systems

    混合bist核系統的測試時間最小化
  13. Hey, little boy. wie alt bist du, huh

    嘿，小男孩.你多大了，哦
  14. Gary bist is a technical writer at ibm s toronto lab

    Gary bist是ibm多倫多實驗室的專職技術作家。
  15. Gary bist is a staff technical writer at ibm s toronto lab

    Gary bist是ibm多倫多實驗室的專職技術作家。
  16. Fast test cost calculation for hybrid bist in digital systems. euromicro symp

    為了避免窮盡式搜索，一種評估確定型測試開銷的方法被引入。
  17. Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip, the construction and application of asip is also analyzed. the fourth chapter introduces the design flow using eda tools based on standard cell, then it presents the dft of this chip in detail which uses following techniques : full scan, bist and boundary scan to improve the fault coverage

    第四章，在對本晶元的基於標準單元eda設計流程進行了簡要說明基礎上，對本晶元採用的可測試性設計進行了詳細的分析和說明，本晶元中有機結合了多種可測試性設計技術：基於全掃描的方式、 bist測試技術、邊界掃描技術，保證了很高的測試故障覆蓋率。
  18. From the view point of the foundation of dft ( which includes the testable measure of gate - level circuits, the testable and controllable measure of functional - level, the flow and methodology of dft and so on ), the author introduce some common testing technology such as scan and bist in modern times. especially the boundary scan technology has been widely adopted in the dft of vlsi. with the special controller, the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports, and the response could also be shifted to the testing output ports

    本文從可測性設計的基礎理論出發（包括門級電路的可測性測度、功能級上的可測性和可控性、可測性設計的流程和方法等） ，介紹了現代常用的可測性技術，比如：掃描技術、內嵌自測試技術等，特別是邊緣掃描技術已經廣泛地應用到vlsi的可測性設計之中，它通過特定的控制器，從相應的測試輸入埠將測試向量掃描至芯核所對應的管腳，再將結果從相應的測試輸出埠掃出。
  19. 15 jervan g, eles p, peng z et al. test time minimization for hybrid bist of core - based systems. asian test symposium, xian, 2003, pp. 318 - 323

    最終，基於我們的評估方法，我們提出一個迭代演算法，該演算法在滿足內存大小約束的同時最小化了測試時間。
  20. Then, the thesis, based on march c - algorithm, shadow read and shadow write technologies, put forwards bist arithmetic for the 20 - port register file

    之後本文在marchc -演算法的基礎上，結合shadowread和shadowwrite技術，首次提出了針對20埠寄存器文件的bist演算法。
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