buffer module 中文意思是什麼

buffer module 解釋
緩沖模塊
  • buffer : n 1 【機械工程】緩沖器,緩沖墊;阻尼器,減震器;消聲器。2 【化學】緩沖,緩沖劑。3 緩沖者;緩沖物...
  • module : n. 1. 測量流水等的單位〈1秒100升〉。2. 【建築】圓柱下部半徑度。3. 【物理學】模,系數,模數,模量。4. 【無線電】微型組件;組件;模塊。5. (太空船上各個獨立的)艙。
  1. Based on vc and opengl software platform, as a part of integrate planar mechanism analysis and simulation cai, the mechanism theory has been adopted to analysis the movement trace and profile of linkage ; adopt oriented object method to capsulate the class module. each corresponding class module complete parameter storage and process ; adopt message - map, message - trigger to organize the programming and response the user " s input ; use the document - view structure of the visual vc + + mfc class foundation as the basis of the programming architecture to complete those functions. use oriented object method to product the following class module : control class, render class, document class, mechanism class and other classes ; adopt opengl library to draw the three dimensional graph based on the result of mechanism analysis ; use model transforming, lighting, material, color, frame - buffer, display - list, graphics - component combine etc to draw the three - dimension mechanism and make the simulation of linkage has high reality

    本文敘述了平面連桿機構運動分析和可視化模擬的理論演算法及其編程實現方法,基於微機vc平臺,採用opengl圖形庫編程,利用面向對象的方法對機構進行功能封裝,利用vc + +的文檔視結構作為最基本的窗架,生成並控制三維繪制類、文檔類、主窗口類和一些輔助類,利用windows平臺的消息映射、事件驅動來組織程序運行和響應用戶反饋,利用機構分析得出坐標數據驅動opengl庫繪制三維機構圖形。
  2. The design of each functional module, including the bridge selected module, mlb slave state machine, buffer, ahb master state machine, arbiter. 4

    各功能模塊的設計,包括橋選擇單元、 mlb從狀態機、緩沖區、 ahb主狀態機,仲裁器; 4
  3. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議( epp )與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上,給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計,其中,對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖,包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後,給出了測試結果,對研製工作做了總結,對本設計的優缺點各做了評述。
  4. The main function modules discussed in this paper include : stream media protocols application model and realization, ts parsing module, audio / video decoder, audio / video synchronization model and realization, player memory buffer management module, multi _ task tech under uclinux. we also discuss the difference of the realization of stream media player between two defferent service types : broadcast tv ( btv ) and video - on - demand ( vod )

    從功能上,流媒體播放器主要包含幾個大的功能模塊:流媒體協議棧的應用模型及實現機制、多節目復用傳輸流( ts )的解析實現、音視頻媒體數據的解碼、音視頻同步機制的設計和實現方法、播放器內存管理模型的設計和實現、 uclinux下多任務的實時調度和高效數據交互技術等。
  5. Secondly, the dynamic storage module designed by our institute is used to design the buffer of the module, which provids the mass storage space for data acquisition, simplifies the design of circuit board and control circuit of the module, meanwhile, provides the solution to the application of huge capacity continuous acquisition

    2 .在模塊的緩存設計上採用所內自行研製的大容量動態存儲模塊,為數據採集提供了大量的存儲空間,簡化了模塊電路板和控制電路的設計,同時,也為大容量連續採集應用提供了解決方案。
  6. Quite a lot of new ideas for designing both logic structure and scheduling structure of the open architecture cnc system have been implemented, including the principles of module - classification, large buffer mechanism for data transfer between modules, principles of time - allocation scheduling, and etc. based on the software structure, the author implemented a few function - modules, such as master - control, interface, decode, interpolation, position - control

    本文在系統的邏輯架構設計和時序架構設計方面做了不少創新性的工作:提出了開放式數控系統的模塊劃分原則,設計並實現了模塊間的大緩沖機制;提出了開放式數控系統的時序設計原則,提出了rtlinux環境中的數控系統時序實現機制並給出了具體方案。
  7. With a combination of the design principles and characteristics of pdsn, a method for compressing data packet using mppc compressing algorithm is put forward. after studying ppp protocol and mppc compressing standards, an algorithm using packet matching sliding window buffer to code and decode is provided. considering not making a great change of current pdsn system, a mppc compressing module is designed and the function to compress data packet through vxworks platform is implemented

    作者首先闡述了pdsn系統的工作原理和系統結構,對移動用戶與pdsn之間的數據傳輸進行了分析,並結合pdsn系統的設計原理和特點採用mppc壓縮演算法對數據報文內容進行壓縮;然後闡述了ppp ( pointtopointprotocol :點對點協議)協議和mppc壓縮標準,採用報文匹配的滑動窗口機制進行編碼和解碼;接著考慮在不對現有pdsn系統進行大改動的基礎上,設計了mppc壓縮模塊,並基於vxworks系統平臺實現了對數據報文內容壓縮的功能;最後對壓縮功能進行了測試並給出測試數據。
  8. In the dissertation , we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels , 8 - bit digitization at rates up to 13. 5mhz 。 frist , the architecture of the video data acqusition system is studied 。 then , the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中,利用cpld的在系統可編程( isp )技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊,用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集,採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  9. The main characters of the design are summarized as follow : 1. each mmdb module is mapped with a data buffer which is used to track the unsynchronized record. when system uploads the data to the mmdb, our system will adopt the round - robin fashion to distribute the data to each module, thus could effectively reduce the load of the foreground system

    針對上述難點採用以下方式對系統進行了優化,有效的保證系統的實時性和可靠性: 1 .數據上載時採用失步緩沖區和內存庫一一對應的關系,對每個內存數據庫數據定時循環上載,減少對單個數據庫的負荷,有效的控制上載流量和速度,防止在上載數據過程中系統負荷過大影響業務操作。
  10. With regard to the buffer storage of the module, a new method called two - lever buffer structure is adopted, in which the fpga ‘ s internal ram cells is the first level buffer and the sdram of embedded system is the second level buffer

    2 .在設備的緩存方案上採用二級緩沖結構,利用fpga內部提供的存儲器單元作為第一級緩沖,利用嵌入式系統中的sdram作為第二級緩沖,實現了多通道、大規模緩存技術。
  11. In this paper, the streaming media technology applied to network video monitor system are researched on the basis of video streaming. the emphases are put on system design, video captures and play, and the design of network transmission module and relevant software development method. in fact, uality of service of the network has unstable characteristics, we have analyzed qos guarantee strategy in video streaming transmission on network, and presents a integrated qos guarantee scheme which based on data encapsulation, buffer storage technology and congestion control on network. this scheme do its best to avoid the big delay or congestion on network based on make full use of network bandwidth, which can guarantee the best qos of the video transmission

    重點討論了系統架構、視頻捕獲和播放、網路傳輸模塊設計以及相關軟體開發方法。同時,針對實際網路中存在的服務不穩定性特點,分析了視頻流在網路傳輸過程中的qos保證技術,並在系統中提出了基於數據封裝、緩存技術以及網路擁塞控制機制的綜合qos解決方案。該方案使系統在充分利用網路帶寬的情況下最大程度上避免出現大的延遲或擁塞,保證了視頻傳輸的最佳服務質量。
  12. In the internet, packet - dropping - based buffer mangement algorithm is an important module in a packet - forwarding device. by employing the buffer management algorithms, ( 1 ) tcp flows can be protected, ( 2 ) without per - flow queueing, the bandwidth of unresponsive and responsive flows can be balanced even with fcfs ( first - come - first - served ) scheduler, ( 3 ) based on per - flow queueing, the bandwidth of unresponsive and responsive flows, as well as that of pure responsive flows can be balanced at the same time, and ( 4 ) in a multi - priority network, different bandwidth can be allocated according to a predetermined proportion

    Internet中,基於分組丟棄技術的緩存管理演算法是分組轉發設備的一個重要的功能模塊,利用它, ( 1 )可以保護tcp流, ( 2 )可以在採用fcfs (先到先服務)調度演算法時較公平地分配響應流和非響應流的帶寬, ( 3 )可以在按流排隊的基礎上同時較公平地分配響應流和非響應流、以及響應流之間的帶寬, ( 4 )還可以在多優先級的網路環境中,根據預定的比例分配帶寬。
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