buffer output 中文意思是什麼

buffer output 解釋
緩沖區輸出
  • buffer : n 1 【機械工程】緩沖器，緩沖墊；阻尼器，減震器；消聲器。2 【化學】緩沖，緩沖劑。3 緩沖者；緩沖物...
  • output : n. 1. 產量；生產，出產，產品。2. 【醫學】（糞便以外的）排泄物；排泄量。3. 【電學】發電力，輸出功率；供給量。4. 輸出信號。
  1. Based on the dsp development board, the author finishes the hardware debug about the multi - channel buffered serial port ( mcbsp ) receiving the output signal from the gps if collector and resolves the software program of the receiving buffer of the multi - channel synchronous serial data, data integration, udp datagram encapsulation and network interface driver, etc. the real - time udp datagram receiving, data frame de - encapsulation and high speed data memory are implemented, and a friend application interface with windows message is developed on the pc

    基於dsp開發板，作者完成了dsp的多通道緩沖串口（ mcbsp ）接收gps中頻接收機輸出信號的硬體調試，並解決了多通道同步串口數據的接收緩沖、數據合併、 udp數據報裝幀及網路介面驅動等軟體編程。在pc端，通過mfc的網路應用開發類casyncsocket實現udp報的實時接收、數據解幀譯碼、高速存貯，利用windows消息機制開發了應用程序友好界面。
  2. By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability

    然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。
  3. At first, 1. 67 u g per well mcab all was coated on three wells of a plate, and then 1. 5 x 1011 phage virion was diluted and added, after incubating with the target, wash away unbound phage by tbst ( 0. 1 % tween - 20 ), the bound phage was eluted with ph 2. 2 tris - gly buffer and amplified, the specially bound phage was enriched by taking through addition binding / amplification cycles. ln the following cycles, the stringency of panning can be increased by raising the concentration of tbst or decreasing that of mcab all, collecting and titering the washing phage of last time and output phage in each round, the selective ratio and the false positive rate of each round were worked out, the gradually increasing of selective ratio and decreasing of positive rate shows that the panning was effective. after 4 rounds of panning, 11 phage clones were selected after competitive - ellsa, the dna samples of 8 positive clones and 1 negative clone were sequenced and all the foreign peptides inserted was also deduced, a clear consensus binding sequence emerged

    在本實驗中，利用隨機12肽庫對抗豬瘟病毒（ classicalswinefeverviruscsfv ）糖蛋白me2的單抗a11進行表位篩選，經過四輪篩選以後，隨機挑取11個克隆作競爭- elisa檢測，結果表明，所挑11個克隆中，有9個克隆能對me2蛋白和a11反應產生抑制作用，抑制率最高可達64 ； dna測序以後經過dnastar軟體分析，發現它們的核心序列為anwralsl ，該核心序列與豬瘟病毒e2蛋白的28 - 35位氨基酸ttwkeysh具有同源性；夾心- elisa檢測和western - blotting試驗均證明所挑陽性克隆能被a11所識別；人工合成含核心序列的多肽經間接elisa試驗證實，也能被a11識別。
  4. Every column in sensor array work in parallel and have their own cds noise reducing circuit. the signals after fpn reducing are output from the output buffer amplifiers

    傳感陣列中各列感光單元的傳感信號并行輸出，分別由對應的相關二次采樣電路進行降噪處理，去除固定模式噪聲后的信號通過輸出緩沖放大電路進行輸出。
  5. The correlated double sampling ( cds ) circuits structure is used to reduce the fixed pattern noise ( fpn ) of the cmos sensors, and improve the signal - noise ratio ( snr ). the 256 photodiodes arrayed 4 quadrants sensor consists 16x16 active photodiodes array. correlated double sampling processing circuits, output buffer amplifiers and digital control part

    針對cmos製造工藝中mos器件固定模式噪聲（ fixedpatternnoise ， fpn ）較大的不足，研究中採用了相關二次采樣（ correlateddoublesampling ， cds ）電路降低固定模式噪聲，從而提高了傳感器的信噪比（ signalnoiseratio ， snr ） 。
  6. Because of block in head of line ( hol ), input buffer strategy make the whole switch system performances declining drastically at heavy oflbred load, and some improvements of input buffer strategy are put forward to overcoming tlle head of line block. virtual output queues ( voq ) is chosen as input buffer strategy. dpa and ilqf ce1l scheduling algorithms for voq are silllulated

    由於輸入緩存的隊頭阻塞使得高負載條件下輸入緩存策略的交換系統各方面性能急劇下降，由此提出了克服輸入緩存隊頭阻塞的改進方法，最後本文決定選用虛擬輸出隊列（ voq ）的輸入緩存策略，並且研究了與虛擬輸出隊列相對應的ilqf （最長隊列優先）和dpa （對角線優先）信元調度演算法，為交換系統的asic設計提供依據。
  7. During this time, line buffer 2, which was presumed to be full, will empty itself into the output paths, on the right of the illustration.

    這時，行緩沖器2假定是滿載的，則向圖右邊的輸出通道卸載。
  8. This paper presents a theoretic analysis of the temporal characteristics of output buffer in switch, gives the probability distribution function of delay and average queuing time, and compares the end - to - end delay between traditional and switched ethernet. vlan is one of important technologies that switch has to implement. switch has to rapidly and efficiently find and maintain an un - looped topology

    在建立交換機的延遲模型基礎上，推導出輸出緩沖延遲分佈、隊列大小等特性；接著比較傳統總線型以太網和交換式以太網的端到端延遲，為交換機以及交換式以太網的設計和分析提供可靠的理論基礎。
  9. Object is used to access the output buffer for sending content directly to the output stream

    對象訪問輸出緩存以直接向輸出流發送內容。
  10. Clears all content output from the buffer stream

    清除緩沖區流中的所有內容輸出。
  11. Today i think my mind is becoming clear about the depth - buffer algorithm after i was pushed to give a clear definition of input and output. indeed, let s note down this : " well defined, well designed ". suddenly i see the essence of " sweeping line " algorithm

    黃教授看著那塊三層肉心頭一陣火起，氣呼呼道： 「這個老婊子丟人現眼，給人倒貼不說，還放話說要跟婆家在家門口決戰，真不要臉，祖宗不幸啊，養下這么個賤貨把老黃家的臉都丟盡了！
  12. Ibis 3. 2 electronic design automation libraries - input output buffer information specifications ibis version 3. 2

    電子設計自動化程序庫.輸入輸出緩存信息規范
  13. Ibis 3. 2 electronic design automation libraries - part 1 : input output buffer information specifications ibis version 3. 2

    電子設計自動化程序庫.第1部分:輸入輸出緩沖器信息規范
  14. Creates a newly allocated byte array. its size is the current size of this output stream and the valid contents of the buffer have been copied into it

    新創建一個過渡性的瞬態的位元組數組，這個數組的大小是輸入流在緩沖中當前的大小，內容是輸入流在緩沖中當前的內容，這個方法執行后，當前輸入流的緩沖被重置。
  15. Electronic design automation libraries - part 1 : input output buffer information specifications, version 3. 2

    電子設計自動化圖書館.第1部分:輸入輸出緩沖信息規范
  16. The current in the dac ’ s output can drive the load, and the structure can save a buffer consisted of operational amplifier, so the structure can achieve high speed with no close - loop and feedback in this circuit

    該10位分段式電流舵型數模轉換器的輸出端可直接用電流輸出來驅動負載阻抗，省去運算放大器構成的輸出緩沖，整個電路中沒有形成閉環和反饋，因此這種電路結構可以達到很高的速度。
  17. Each virtual - loop ' s output signals are recorded in its special data buffer, which is updated when processing every frame. through observing the digital string of each

    每個虛擬線圈都擁有自己的數據緩沖池而不會造成多線圈間的數據訪問混亂，數據緩沖池中的數據是逐幀更新的。
  18. Because of the complexity of this program, we only consider the optimization design about output buffer in the program, so as to obtain performance analysis of output buffer

    由於此設計方案的復雜性，我們只是對輸出端緩沖庫進行行為分析。
  19. Gets or sets a value indicating whether to buffer output and send it after the entire page is finished processing

    獲取或設置一個值，該值指示是否緩沖輸出，並在完成處理整個頁之後將其發送。
  20. Gets or sets a value indicating whether to buffer output and send it after the entire response is finished processing

    獲取或設置一個值，該值指示是否緩沖輸出，並在完成處理整個響應之後將其發送。
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