buffer ram 中文意思是什麼
buffer ram
解釋
緩沖桿-
It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks
在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。 -
The proposed project that using the duel - port ram inner fpga as data buffer has greatly simplified the design process and enhanced the system performance
本設計中提出的利用fpga內部雙口塊ram構成數據緩存的實現方案大大的簡化了設計並提高了系統性能。 -
We can take dsp to realize fast encryption algorithm because of its highly parallelism, application - specific hardware logic, and application - specific instructions. pci transaction and dsp processing of data can take place simultaneously for its dual - access ram ( daram ) and host port interface ( hpi ). and, the time taken for interruption almost can be ignored because of deep buffer technology
Dsp具有高度的并行結構、專用硬體邏輯以及許多專用指令，可以實現快速加密演算法， dsp的雙訪問ram （ daram ）和主機并行介面（ hpi ）可以實現數據pci傳送和dsp處理同時進行，另外採用了深度緩沖技術，使花在主機中斷上的時間幾乎可以忽略不計，所以基於dsp的計算機數據加密卡pcijmc2000獲得了較高的處理速度。 -
The branch target buffer is provided with a tag ram that is organized in a set associative fashion
分支目標緩沖器提供一個架構成集合相關式的標簽記憶體。 -
They can be effectively shelved in a small ram - based waiting instruction buffer and steered into the iq at appropriate time. with this two - level shelving ability, half of the cam tag comparators are eliminated in the iq, which significantly reduces the energy of wakeup operation
通過類似於分支方向預測的技術稱為last - tag prediction ，可以將每個cam表項中的比較器由2個減少為1個，從而降低喚醒邏輯的能耗。 -
With regard to the buffer storage of the module, a new method called two - lever buffer structure is adopted, in which the fpga ‘ s internal ram cells is the first level buffer and the sdram of embedded system is the second level buffer
2 .在設備的緩存方案上採用二級緩沖結構，利用fpga內部提供的存儲器單元作為第一級緩沖，利用嵌入式系統中的sdram作為第二級緩沖，實現了多通道、大規模緩存技術。 -
Industrial buffer cutting processing and marketing of packaging materials : ram pieces, metal pieces for processing
工業緩沖包裝材料的切割加工及銷售：沖壓件、五金件加工。
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