built-in self test 中文意思是什麼
built-in self test
解釋
內建自測試-
Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ), boundary scan and internal scan
Jx5微處理器的測試結構由bist 、邊界掃描和內部掃描三部分組成。 -
In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result, the fault coverage is more than 96 %
本文針對嵌入式微處理器estar1的結構特點，研究並實現了邊界掃描、內部全掃描和內建自測試三種可測性設計技術，取得了良好的效果，故障覆蓋率達到96以上。 -
Not only the scan route solution, the built - in self - test solution and the boundary scan solution of design for testability are summarized, but also the applications and countermeasures of these 3 solutions are analysed and compared in details
摘要綜述了超大規模集成電路的幾種主要的可測試性設計技術，如掃描路徑法、內建自測試法和邊界掃描法等，並分析比較了這幾種設計技術各自的特點及其應用方法和策略。 -
Built - in power on self test
內裝的自測試電源 -
And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned
Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。 -
Built - in self - test of logic blocks in fpgas finally, a free lunch : bist without overhead !. in proc. vlsi test symp.,
對於一個具有4輸入lut的fpga來說，這與lut測試需要8次配置形成了鮮明的對比。 -
4 stroud c, wijesuriya s, hamilton c, abramovici m. built - in self - test of fpga interconnect
在第一個階段，一些le包含著cut ，而且其他的le包含著bist體系結構。 -
The advantages of the two methods are combined together in the pseudo - random current injection testing method, which improves the efficiency and correctness of the test, and which is much more operable, thus it is very applicable in built - in - self - testing of analog and mixed signal circuits in system chips
偽隨機注入電流測試法結合了兩種方法的優點，提高了測試的效率和正確性，實現時簡單易行，非常適合於系統晶元中對模擬及混合信號電路的內建自測試。
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