bus interface timing 中文意思是什麼

bus interface timing 解釋
總線介面時序
  • bus : n (pl busses buses)1 公共馬車;公共汽車;客機。2 〈口語〉汽車,機器腳踏車;飛機。3 【電學】信息...
  • interface : n. 分界面,兩個獨立體系的相交處。vt. (-faced, -facing) 把界面縫合。vi. 交流,交談。
  • timing : n. 1. 時間選擇。2. 定時,校時,計時,調速。3. 【自動化】同步;時限。
  1. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象,在詳細分析原設備的系統結構和功能實現方式的基礎上,指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題,同時結合系統的低功耗需求和優化人機介面設計,本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案:在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路; cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計;基於低功耗設計的器件選型方案和單片機待機模式設計;人機介面的lcd菜單操作方式。
  2. System control module accomplishes many functions, such as systemic initialization, controling work of the system, man - machine interface and selecting channel. it communicates with other modules by i2c bus. timing signals are inputed into microprocessor through p1 port and control signals are provided through p2 port

    系統控制模塊和其他模塊間的通訊基於i ~ 2c總線,並利用了p1口進行各時鐘信號的檢測和利用p2口的各線作為控制線宋控制相應模塊的工作。
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