cascode 中文意思是什麼

By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability

然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。

For the demand of output swing, the bias is provided by high - swing cascode current mirrors

為了獲得高輸出擺幅，設計低壓共源共柵電流鏡為運放提供偏置。

On the one hand, the design uses low voltage cascode op framework to improve its gain ; on the other hand, it applies self - bias and cascode structure to the whole sensing circuit. by using the improved method, we have successfully obtained low power consumption, low offset, high linear and high psrr ptat current generator under low power supply

在電路設計上一方面改進運放結構，採用低壓共源共柵結構以提高其增益，另一方面整體傳感電路採用自偏置結構和共源共柵電流鏡結構，在低電源電壓下成功設計了低功耗、低失調、高線性度和高電源電壓抑制比的ptat電流產生電路。

2. the input stages of the ccii and the operational amplifier in transimpedance implifier are realized with folded cascode amplifier to reach high cmrr, large open loop gain and low offset

2 .為了提高儀表放大器的電源抑制比，並得到大的開環增益，相對低的失調等性能，電流傳輸器的輸入級和跨阻放大器中運算放大器輸入級均採用折疊共源共柵放大器。

The main research content about this two subcircuits are as follows : 1. the precision and dynamic range of several typical current mirrors are discussed and an active input regulated - cascode output current mirror is adopted as the current duplicate circuits in ccii

在這兩個子電路中主要進行了如下研究: 1 .研究了幾種常用的電流鏡的電流傳輸精度和動態范圍，並最終選擇有源輸入校準型電流鏡作為電流傳輸器中的電流傳輸電路。

The thesis has done the widespread investigation and study to the domestic and foreign ’ s technologies of analogy low voltage and low power, and analyzes the principles of work, merts and shortcomings of these technologies, based on the absorption of these technologies, it designs a 1. 5v low power rail - to - rail cmos operational amplifier. when designing input stage, in order to enable the input common mode voltage range to achieve rail - to - rail, it does not use the traditional differential input pair, but use the nmos tube and the pmos tube parallel supplementary differential input pair to the structure, and uses the proportional current mirror technology to realize the constant transconductance of input stage. in the middle gain stage design, the current mirror load does not use the traditional standard cascode structure, but uses the low voltage, wide - swing casecode structure which is suitable to work in low voltage. when designing output stage, in order to enhance the efficiency, it uses the push - pull common source stage amplifier as the output stage, the output voltage swing basically reached rail - to - rail. the thesis changes the design of the traditional normal source based on the operational amplifier, uses the differential amplifier with current mirror load to design a normal current source. the normal current source provides the stable bias current and the bias voltage to the operational amplifier, so the stability of operational amplifier is guaranteed. the thesis uses the miller compensate technology with a adjusting zero resistance to compensate the operational amplifier

本論文對國內外的模擬低電壓低功耗技術做了廣泛的調查研究，分析了這些技術的工作原理和優缺點，在吸收這些技術成果基礎上設計了一個1 . 5v低功耗軌至軌cmos運算放大器。在設計輸入級時，為了使輸入共模電壓范圍達到軌至軌，不是採用傳統的差動輸入結構，而是採用了nmos管和pmos管並聯的互補差動輸入對結構，並採用成比例的電流鏡技術實現了輸入級跨導的恆定;在中間增益級設計中，電流鏡負載並不是採用傳統的標準共源共柵結構，而是採用了適合在低壓工作的低壓寬擺幅共源共柵結構;在輸出級設計時，為了提高效率，採用了推挽共源級放大器作為輸出級，輸出電壓擺幅基本上達到了軌至軌;本論文改變傳統基準源基於運放的設計，採用了帶電流鏡負載的差分放大器設計了一個基準電流源，給運放提供穩定的偏置電流和偏置電壓，保證了運放的穩定性;並採用了帶調零電阻的密勒補償技術對運放進行頻率補償。

Based on the study of circuit cells which are applied in sige bicmos operational amplifier, the telescope cascode configuration is selected to realize high speed and high gain

其次，通過對sigebicmos運算放大器中電路單元的研究，並結合運放實際設計指標，選擇套筒式共源共柵結構作為運放的主體結構以確保高速、高增益的實現。

The traditional bandgap reference circuit was improved in the design, which includes the applying of self - bias structure and cascode structure, output of the opamp was used as self - bias voltage, saving bias circuit, and then it was helpful to get low power consumption. through using poly resistance of high value with low temperature coefficient, we reduced the influnce to circuit, if power supply did not change, we must decrease operating current to decrease power consumption, and increasing value of resistor could decrease the operating current efficiently. poly resistance of high value had large value of squared resistor, so we could save layout area

對傳統帶隙基準電路進行了改進設計，採用自偏置結構和鏡像電流鏡結構，利用運放的輸出電壓作為運放的偏置電壓，節省了偏置電路，降低了功耗;使用低溫度系數的多晶硅高值電阻，降低了電阻溫漂對電路的影響;在電源電壓不變的情況下，為了減小功耗就必須減小工作電流，而增大電阻的阻值能有效地減小工作電流，多晶硅高值電阻的方塊電阻很大，可以節省版圖面積。

The lna with source inductor degeneration is analyzed in detail, which is used most widely in current. base on the analysis, a cascode structure is presented to minimize the effect of gate - drain capacitance cgd

針對目前lna中應用最廣泛的源極電感負反饋結構，進行了詳細分析，在此基礎上對該結構做出了優化，採用共源共柵級聯結構，減小了柵漏電容cgd的影響。

The drive stage is made up of cascode class - f topology. a “ big ” mosfet is used in the class - e output stage. the thesis did the simulation of the pa by ads with the tsmc 0. 18 m rf cmos model, and completed the layout of the pa

本文設計了一種新穎的射頻cmos功率放大器，採用兩級差分結構，用f類共源共柵結構作為驅動級，輸出級採用大尺寸mos管的e類功率放大器。

In this paper, the traditional cascode structure of cmos lna is considered as a two - stage amplifier and inter - stage matching network is introduced accordingly

本文也對cmos低噪聲放大器進行了分析，將傳統共源共柵結構看作二級放大器級聯形式，並由此引入級間匹配網路。

Based on the volterra series, expressions describing the third - order intermodulation distortion in cmos cascode lnas are derived

基於伏特拉級數，本文推導出了描述cmoscascode結構低噪聲放大器三階互調指標的方程。

Cascode transistor circuit

串聯晶體管電路

Techniques for optimizing the cascode transistor are proposed

我們給出了對cascode場效應管的優化方法。

The impact of the cascode transistor on the noise and linearity performance of the cmos lna is discussed in detail

本文詳細分析了cascode場效應管對cmos低噪聲放大器的噪聲和線性性能的影響。

By taking the capacitance into consideration, we show new noise figure optimization methods for cmos cascode lnas

在考慮了該電容以後，本文給出了新的cmoscascode結構低噪聲放大器的優化方法。

According to the analysis of the whole communication system, we verified the feasibility of the design goal put forward previously and used a topology of cascode with source degeneration to design a differential lna

通過對衛星通信系統的鏈路分析，根據實際系統需要，確定了低噪放模塊的設計指標。採用常用的共源共柵拓撲結構，設計了一個差分結構的lna 。

The full noise and linearity analysis of the low noise amplifier ( lna ) constructed by cascode structure with source degeneration and the optimization methods of the two mosfets in this structure according to the noise and linearity performance

I對共源共柵矚ascode ）源極去耦舊ourcedegeneration ）結構低噪放做了完整的噪聲和線性分析，得到該結構中兩個mosfet針對噪聲性能和線性性能的優化方法。