clock cycle 中文意思是什麼

clock cycle 解釋
時鐘脈沖周期
  • clock : n 1 鐘;掛鐘,座鐘,上下班計時計。2 〈俚語〉記秒錶,卡馬表;〈美俚〉〈pl 〉駕駛儀表,速度表,里程...
  • cycle : n 1 循環,周期,一轉。2 周時,周年,年紀。3 (詩、故事等的)始末。4 自行車,三輪車,摩托車。5 【...
  1. Tinkering with the circadian clock, the day - and - night cycle in the physiological processes of all living beings, is rarely a good idea

    搗亂生物鐘? ?萬物生靈生理過程中的晝夜節律? ?絕不是個好主意。
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長,通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法,加快了微處理器的速度,提高了指令的執行效率。
  3. All the works are made by selectively usage of the systematic strategic management theories and methods, including pest macro environment analysis theory, porter ' s " five forces " model, industry cycle theory, market structure theory, strategic group analysis, competitive advantage framework and composition theory of the created value by enterprises, financial ratio analysis, value chain analysis, bcg matrix, swot analysis, strategy clock

    本文在研究過程中使用了pest宏觀環境分析理論、波特的「五力」模型、產業周期理論、市場結構理論、戰略群體分析、競爭優勢框架及企業創造價值的構成理論、財務比率分析、價值鏈模型、波士頓矩陣、 swot分析、戰略鐘等理論和方法。力求透徹分析從而得出正確的結論。
  4. The design team s goal was to complete one instruction per clock cycle, and to accommodate 300 calls per minute

    設計小組的目標是在每個時鐘周期內完成一條指令,從而每分鐘可以處理300個電話。
  5. Based on analysis, we finished the architecture design and the division of the functional modules. allowing for the pic16c57 mcu can not suit the high speed situation, we improving the clock structure through using one clock instead of the original four clock technology. cooperating the instruction work step, the new clock structure executed one clock cycle per instruction

    針對pic16c5x系列微控制器不能適用於高速場合的需要,對其時序結構進行了改進設計,用單時鐘代替原來的四相時鐘技術,採用二級流水結構,配合指令的工作節拍,使指令執行周期縮短為單個時鐘周期。
  6. Each machine cycle takes 12 oscillator or clock cycles

    每個機器周期為12個振蕩器或時鐘周期。
  7. Ipc instructions per clock cycle

    指令時鐘周期
  8. The data in sam will be read out during the hind half of the clock cycle

    後半個時鐘周期則是對sam中的數據進行讀取。
  9. But because all instructions completed in one clock cycle, it lacked floating - point and superscalar parallel processing ability

    但是由於所有的指令都必須在一個時鐘周期內完成,因此其浮點運算和超量計算(并行處理)能力很差。
  10. Melatonin production by the pineal gland is determined by the amount of light received, for the gland plays the role of a bodily clock, due to its sensitivity to light and regulation of the sleep - wake cycle

    松果體會根據所接收到的光量多少來決定褪黑激素分泌的量,藉由對光的敏感度,松果體充當了人體內的一個時鐘,掌控著每天蘇醒和睡眠的時間。
  11. All the 32 registers are directly connected to the arithmetic logic unit ( alu ), allowing two independent registers to be accessed in one single instruction executed in one clock cycle

    所有的寄存器都直接與算邏單元( alu )相連接,使得一條指令可以在一個時鐘周期內同時訪問兩個獨立的寄存器。
  12. And some effective techniques are discussed to lower the clock period and cpi ( cycles per instruction ) of the pipeline. to eliminate the clock frequency limitation by some complex instructions " long executing time and achieve single - cycle throughput, a scalable super - pipelining extension technique together with a high performance / cost pipeline shift mechanism is presented in this paper

    為避免流水時鐘頻率受制於某些復雜運算指令較長的運算時間,又要達到單周期完成一條運算指令的吞吐量指標,本文提出對ex級進行可伸縮超流水擴展的思想,提出並實現了一種高性加比的切換控制方案。
  13. Every pixel generates a bit data after front half of the clock cycle, then the pixel array generate a bit plane which is stored in sam

    每半個時鐘周期結束后每個像素就會產生一位數據,整個像素組就產生了一個位平面( bitplane ) ,存儲在sam中。
  14. A mac unit has been specially optimized and can complete a 32 - bit mac operation within one clock cycle of 5ns. we analyze the multiplication procedures and find out the obstacles to improve the speed. to accelerate the multiplication operation, a modified booth structure has been used to reduce the number of partial products

    在分裂式alu設計工作中,提出了三種方法解決時延問題: (一)具體分析關鍵路徑中決定時延的關鍵信號,優化其相關邏輯電路,提高速度,減小模塊整體關鍵路徑時延。
分享友人