clock design 中文意思是什麼

clock design 解釋
時鐘位置
  • clock : n 1 鐘;掛鐘,座鐘,上下班計時計。2 〈俚語〉記秒錶,卡馬表;〈美俚〉〈pl 〉駕駛儀表,速度表,里程...
  • design : vt 1 計劃,企圖,立意要…。2 指定,預定;留給,留著。3 設計,草擬,擬定,籌劃;起草,畫草圖,打(...
  1. Dundrum, south, or sutton, north, both localities equally reported by trial to resemble the terrestrial poles in being favourable climates for phthisical subjects, the premises to be held under feefarmgrant, lease 999 years, the message to consist of 1 drawingroom with baywindow 2 lancets, thermometer affixed, 1 sittingroom, 4 bedrooms, 2 servants rooms, tiled kitchen with close range and scullery, lounge hall fitted with linen wallpresses, fumed oak sectional bookcase containing the encyclopaedia britannica and new century dictionary, transverse obsolete medieval and oriental weapons, dinner gong, alabaster lamp, bowl pendant, vulcanite automatic telephone receiver with adjacent directory, handtufted axminster carpet with cream ground and trellis border, loo table with pillar and claw legs, hearth with massive firebrasses and ormolu mantel chronometer clock, guaranteed timekeeper with cathedral chime, barometer with hygrographic chart, comfortable lounge settees and corner fitments, upholstered in ruby plush with good springing and sunk centre, three banner japanese screen and cuspidors club style, rich wine - coloured leather, gloss renewable with a minimum of labour by use of linseed oil and vinegar and pyramidically prismatic central chandelier lustre, bentwood perch with a fingertame parrot expurgated language, embossed mural paper at 10 - per dozen with transverse swags of carmine floral design and top crown frieze, staircase, three continuous flights at successive right angles, of varnished cleargrained oak, treads and risers, newel, balusters and handrail, with stepped - up panel dado, dressed with camphorated wax, bathroom, hot and cold supply, reclining and shower : water closet on mezzanine provided with opaque singlepane oblong window, tipup seat, bracket lamp, brass tierod brace, armrests, footstool and artistic oleograph on inner face of door : ditto, plain : servant s apartments with separate sanitary and hygienic necessaries for cook, general and betweenmaid salary, rising by biennial unearned increments of 2, with comprehensive fidelity insurance annual bonus, and retiring allowance based on the 65 system after 30 years service, pantry, buttery, larder, refrigerator, outoffices, coal and wood cellarage with winebin still and sparkling vintages for distinguished guests, if entertained to dinner evening dress, carbon monoxide gas supply throughout

    一截彎木上棲著一隻馴順得能停在手指上的鸚鵡它吐字文雅,墻上糊著每打價為十先令的壓花壁紙,印著胭脂紅色垂花橫紋圖案,頂端是帶狀裝飾一連三段櫟木樓梯,接連兩次拐成直角,都用清漆塗出清晰的木紋,梯級登板起柱欄桿和扶手,一律用護板來加固並塗上含樟腦的蠟浴室里有冷熱水管,盆湯淋浴,設備俱全。位於平臺246上的廁所里,長方形窗子上嵌著一塊毛玻璃,帶蓋的坐式抽水馬桶,壁燈,黃銅拉鏈和把手,兩側各放著憑肘幾和腳凳,門內側還掛有藝術氣息濃厚的油畫式石版畫。另外還有一間普通的廁所廚師打雜的女僕和兼做些細活的女傭的下房裡也分別裝有保健衛生設備僕役的工錢每兩年遞增兩英鎊,並根據一般忠誠勤勞保險,每年年底發獎金一英鎊,對工滿三十年者,按照六十五歲退職的規定,發退職金餐具室配膳室食品庫冷藏庫主樓外的廚房及貯藏室等堆煤柴用的地窨子里還有個葡萄酒窖不起泡亮光閃閃的葡萄酒,這是為宴請貴賓吃正餐身穿夜禮服時預備的。
  2. To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named det ( double - edge - triggered ) shift register is proposed

    摘要從消除時鐘信號冗餘跳變而致的無效功耗的要求出發,提出雙邊沿移位寄存器的設計思想。
  3. Then, we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock

    接著,從消除時鐘信號冗餘跳變而致的無效功耗的要求出發,提出雙邊沿移位寄存器的設計思想。
  4. He was so kind and holy and often and often she thought and thought could she work a ruched teacosy with embroidered floral design for him as a present or a clock but they had a clock she noticed on the mantelpiece white and gold with a canary bird that came out of a little house to tell the time the day she went there about the flowers for the forty hours adoration because it was hard to know what sort of a present to give or perhaps an album of illuminated views of dublin or some place

    49他是那樣的和藹聖潔,她多次想做一隻帶褶飾的繡花茶壺保溫罩送給他。要麼就是一隻座鐘。只是那一天她為了四十小時朝拜50用的鮮花而去那裡時,曾注意到他們的壁爐臺上擺著一隻白金兩色的座鐘,一隻金絲雀從一個小屋裡踱出報時。
  5. Those include power supply circuit design ; ground plane design and sample clock design. combining some radar development, its high - speed a / d circuit is tested, and has given out some test results

    最後結合某雷達研製,對其高速模數轉換電路設計進行了實際測試評估,並給出了部分測試結果。
  6. Such as harmonic distorted in front analog circuit, sample clock shaking, analog power and the noise in ground plane etc. some suggestion of circuit design is given to improve high - speed a / d circuit performance

    在高速模數轉換電路的應用設計中地電源供電設計、模數地平面設計、采樣時鐘設計等方面提出一些具有指導性的意見。
  7. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中,首先介紹模數轉換器的各種參數的意義,以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案,引入級聯結構調制器,特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器,調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計,包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等,並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後,利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  8. Zhangzhou city even to preceded clock and watch co., ltd., design, manu - facture, sell on integrative manufacturer of quartz clock

    漳州市勻冠鐘表有限公司,是集石英鐘設計、製造、銷售於一體的生產廠家。
  9. The u. s. air force tass tactical automated security system program depends on thermovisions rugged design, crystal clear imagery and networkability to keep its installations safe around the clock

    美國空軍tass戰術自動保衛系統程序就取決于thermovision堅固的設計,極其清晰的圖像質量和可連網。
  10. Real time clock system design based on spi

    的實時時鐘系統設計
  11. This paper introduces working principle of tower clock control system in detail from two aspects of hardware and software. some effective anti - disturb measures adopted in design process are explained

    從硬體和軟體兩個方面詳細介紹了塔鐘控制系統的工作原理,並闡述了設計中所採取的一些有效的抗干擾措施
  12. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案,並對其中主要功能模塊和關鍵演算法作出了詳細說明,包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  13. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法,它針對目前工業界較為流行的標準單元布局,應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息,可以通過調整單元位置,更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明,該演算法可以有效地改善合理偏差范圍的分佈,而對電路的其它性能影響很小
  14. They had been working round the clock for a couple of days hoping to get the design out before their competitors did

    他們晝夜不停地幹了幾天,希望先於競爭者把設計搞出來。
  15. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析,提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  16. The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity.

    高時鐘頻率的要求比高抗擾度的要求更為重要,因為高抗擾度可通過精心設計予以保證。
  17. High - qualified designers and engineers of chaowei are able to provide various high - qualified design services such as ic software program, circuit board, product appearance, products structure, and product package, etc. the factories directly under chaowei have advanced production abilities including mould making, inection moulding, surface spray - painting, silk - screening, shift - screening, smt, welding and assembling, quartz clock core production, and quality check and assurance. chaowei held many design patents and utility model patents, at the same time, national clock and watch quality certification, national technical supervision bureau certification, usa fcc and astm security authentication, canada ic, and euro ce are achieved, the rich experience in oem and odm can ensure high quality products and professional service

    超維公司擁有一批高素質的專業設計師和工程師,有能力為國內外客戶提供包括ic軟體編程線路板設計產品外觀設計產品結構設計產品包裝設計等多方面高水準的設計服務超維的直屬工廠則擁有模具製造注塑成型表面噴漆絲印移印smt焊接裝配石英鐘機芯製造品質檢驗測試等先進的生產能力超維公司的產品擁有大量的外觀設計專利和實用新型專利,同時獲得了國家鐘表質量檢驗中心的合格證書國家技術監督局檢驗合格證書美國fcc認證和astm安全認證加拿大ic認證歐盟ce認證。
  18. It ' s very convenient to use a scm to design a digital clock with software

    摘要用單片機來設計數字鐘,軟體實現各種功能比較方便。
  19. Combined with the orcad pspice software, it also simulates the clock pulse circuits and relay circuits on the motherboard. the simulation results can satisfy the requirement of the circuit design

    並對母板上的時鐘脈沖電路、繼電器電路應用orcadpspice進行了模擬模擬,模擬結果符合電路設計要求。
  20. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法,並在me演算法基礎上進行改進,創造性的去掉了縮短碼解碼中的校正環節,糾正了有關論文中的不當論述,並將rs解碼模塊進行了參數化設計,同時也將rs解碼的規模縮小了20 ;克服了多時鐘設計中的信號完整性難題,在沒有增加模塊面積的條件下,大幅降低數據的相位摘要抖動,首次引入鎖相環來調整速率。
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