collector to-base resistance 中文意思是什麼

collector to-base resistance 解釋
集電極
  • collector : n 1 收集家；採集者；收集器。2 收稅員；收款員；募捐人；〈美國〉（海關的）徵收員；收票員。3 【電學...
  • to : adv 到某種狀態；〈特指〉到停止狀態；關閉。 ★也常和動詞結合，略去其後賓語，而構成成語： The door i...
  • base : n 1 基底，基，根基，底座；底層，底子；（紀念碑等的）基址；（山）麓。2 【軍事】基地，根據地。3 根...
  • resistance : n. 1. 抵抗，反抗，抗拒，抵禦；敵對，抵抗力，反抗力，阻力，【生物學】抗病性。2. 【電學】電阻；阻抗；電阻器。
  1. First, passive resistance network was selected as direct current biasing network, which offered direct voltage for base through the resistance voltage divider composed of two resistances, among them the upper resistance connected from the dc to base, the lower resistance connected from the base to ground. the collector connected with dc directly

    直流偏置網路採用無源電阻網路，通過由兩個電阻組成的電阻分壓器為基極提供直流電壓，上偏電阻從電源串聯到基極，下偏電阻從基極到地，集電極直接加電。
  2. And the results of calculation and numerical simulation indicate, without increasing the intrinsic collector - junction area of power devices, collector - combed structure helps to raise the intrinsic heat - dissipating area and base ' s perimeter, improve heat - dissipating method of each cell of the chip, enhance the distribution uniformity of junction temperature and current of each cell of the chip, reduce the thermal resistance and raise the dissipation power pd and output power p0, fairly well relax the contradiction among frequency, out - put power and dissipation power of the devices, and further improve the devices " property against second breakdown

    而計算分析和二維數值模擬分析結果表明：梳狀集電結（基區）結構在不增加器件本徵集電結面積的條件下，增大了器件的本徵散熱面積和基區周長，改進了每個子器件單元內的散熱方式，提高了單元內結溫和電流分佈的均勻性，降低了器件的熱阻，增大了器件的耗散功率和輸出功率，較好地緩解了目前傳統結構中頻率與功率、功耗的矛盾，並有利於改善器件抗二次擊穿的性能。
  3. In the experiment we also observed negative differential resistance characteristics of gesi hbts with heavily doped base at high collector - emitter voltage and high current. a new interpretation to this phenomenon was given. this

    在實驗中我們還觀察到，在高vce和大電流下，重摻雜基區gesihbt出現負阻現象，我們對這一現象進行了新的解釋，認為這是由熱電負反饋導致的。
  4. A silicon self - aligned technology was achieved by using a smart power integrated technology to get high power of the circuit. vertical pnp transistor whose base is epitaxy layer was used as output. the collector of the vertical pnp transistor was set on the back of the chip with low resistance p + substrate as ohm contact

    在工藝中，採用了smart功率集成技術實現電路的大功率，基區是外延層的縱向pnp晶體管作為輸出，將集電極置於晶元背面，採用低電阻率p ~ +襯底作為歐姆接觸。
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