control clock 中文意思是什麼
control clock
解釋
控制鐘-
Modern campaign is physiological consider to make clear, the apogee of human body physical strength and nadir suffer airframe " biological clock " control, reach a peak in the dusk commonly
現代運動生理學研究表明，人體體力的最高點和最低點受機體「生物鐘」的控制，一般在傍晚達到高峰。 -
The genes that control the body clock are most active in parts of the brain called the suprachiasmatic nuclei
控制生物鐘的基因在腦部的視交叉上核的細胞內最為活躍。 -
Using domestic strained integrated resistor as weighing sensor, at89c52 single chip as control unit, combined with arithmetical magnification, analogtodigital conversion ( a / d ), real time clock, liquid crystal display ( lcd ), and series communication interface, a minitype automatic weighing lysimeter is developed. that made measurement of evapotranspiration become conveniently and effectively in studying on water use of crops
為了方便、有效地測定植物的蒸散，為水分利用研究提供價廉物美、簡單易用的儀器，本研究利用國產的集成電阻應變式稱重傳感器，採用at89c52單片機作為控制單元，結合運算放大、模數轉換、實時時鐘、液晶顯示、數據存儲、串列通信等外圍介面電路，研製了小型自動稱重式蒸散儀。 -
This paper introduces working principle of tower clock control system in detail from two aspects of hardware and software. some effective anti - disturb measures adopted in design process are explained
從硬體和軟體兩個方面詳細介紹了塔鐘控制系統的工作原理，並闡述了設計中所採取的一些有效的抗干擾措施 -
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
In this paper, a clock recovery system that based on phase control technology is studied
本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。 -
Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed
其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。 -
Round - the - clock harbour control section round - the - clock western immigration anchorage
全日二十四小時（港口管制組） -
Control multi device with database clock setting mc672a
設定控制板mc672a時鐘 -
Realization of digital clock control system by complex programmable logic device
實現的數字鐘控系統 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
Secondly, based on the function requirement of usb device controller the system was divided into five modules, clock extracting, event detect, physical layer interface, media access controller, endpoint control layer and every module was designed in detail
其次，針對usb設備控制器的功能要求，將系統分為時鐘提取、事件檢測、物理層、介質訪問層、端點控制層五個模塊並對每個模塊進行了詳細設計。 -
Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail
基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter
整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。 -
And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed
本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。 -
The host computer system ' s functions are as follows : duplex communicate with automatic station data poll gather to each automatic station save and handle the data format and print diagram based on the gathered data download the parameter to automatic station and adjust the clock dial - up to network and long - distance control automatic rainfall station consists of outer garment, meet rain bucket, water input and output electromagnetic valve, measure bucket, storage battery and circuit control
可以與自動站進行雙向通訊，完成對各個自動站數據輪詢採集並進行存儲、處理，並生成圖表，根據採集的數據形成圖表、列印，可以向自動雨量下載參數、時鐘校準以及遠程聯網撥號和控制。自動雨量站包括外罩、接雨桶、進放水電磁閥、測量桶、蓄電池以及電控部分等部分組成。 -
This design is the first solid - state memory system for satellite, which can confront with multi - clock sources and multi - data sources compatibly. it is the fist design that integrates all functions of data processing and control into a single programed logic device. this design can be an ip core that can bring large advantage when system upgrade in the future
本星載固存系統是我國星載固存系統中第一個採用多數據源，多時鐘源進行兼容設計的單一固存系統；第一個採用ip化、參數化設計思想，採用單一邏輯編程器件做為固存系統唯一控制部件，為以後系統升級帶來了很大好處；第一個採用功耗均衡思想來降低系統功耗。 -
This is a clock control which is able to roll the digit away as the time elapses, just like what the oil meter does in the old car
這個時鐘控制項可以直接調整經過的時間，就像在老式車中的油表器一樣。 -
Design and implementation of self - control clock based on gps time source
時間源的自控時鐘的設計與實現
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