csmc 中文意思是什麼

csmc 解釋
成電路設計西安產業化基地日前宣布與
  1. China ' s domestic companies included 86 ic design companies : china integrated circuit design co., ltd., datang microelectronics, c * core, spreadtrum communication, lhwt, shenzhen state microelectronics, shenzhen zte ic design, hisense hiview tech., etc. ; 25 manufacturers : smic, huahong nec, hejian, china resources microelectronics, grace semiconductor manufacturing, csmc tech., asmc, etc ; 10 engaged in packaging and testing, such as nantong fujitsu, jiangsu changjiang electronics, tianshui huatian, 10 semiconductor equipment manufacturers : cetc no. 2 institute, cetc no. 48 institute, beijing sevenstar huachuang, institute of microelectronics of the chinese academy of sciences, institute of optics and electronics of the chinese academy of sciences etc. ; 37 semiconductor materials providers, including grinm semiconductor materials, heraeus zhaoyuan precious metal materials, etc

    國內參展商包括中國華大、大唐微電子、蘇州國芯、展訊通信、六合萬通、深圳國微、深圳中興集成電路、海信信芯科技等86家集成電路設計公司；中芯國際、華虹nec 、和艦科技、華潤微電子、宏力半導體、華潤上華、上海新進等25家主要集成電路製造企業；南通富士通、江蘇長電、天水華天等10家封裝測試企業；中電科技集團第2研究所、第48研究所、七星華創、中科院微電子所、中科院光電所等10家半導體設備企業；有研矽谷、賀利氏招遠等37家半導體材料企業。
  2. The circuit was simulated via hspice based on csmc 0. 5um process whose results indicates the all modules have meet the requirements and the efficiency can go up to 95 % under pwm mode and stay above 90 % under pfm mode when the load resistance

    晶元內設過熱保護和欠壓保護，以實現電路的可靠性操作。最後設計電路基於0 . 5 mcomsn阱工藝，用hspice模擬，每個模塊性能都滿足電路要求。
  3. In the meantime, the all sub - circuits are also designed and emulated carefully including inverter, rs type flip - flop, voltage reference circuit, error amplifier, voltage comparator, sawtooth - wave generator, pwm comparator, soft activation circuit and so on. as a result, all of the sub - circuits answer the requirements. this chip has taped out with the 0. 5um mix - signal process of csmc

    本文利用cadenceeda集成電路設計工具、 spectres模擬工具，對集成電路內的各個模塊包括反相器、基本rs觸發器、基準電壓電路、誤差放大電路、電壓比較電路、鋸齒波振蕩發生電路、 pwm比較電路、軟啟動電路、驅動電路等進行了具體的設計和模擬，且達到了預先設定的指標。
  4. In this study, the design procedures for mitigating radiation effects mechanisms have been implemented in a gate array design, we have obtained samples of integrated circuits test structures manufactured by wuxi csmc - hj using their 0. 6 - m cmos process

    在研究中，我們將降低輻射效應的設計方法應用到門陣列設計中，獲得了華晶上華半導體有限公司採用0 . 6 m的cmos工藝生產的集成電路樣片，具有100krad （ si ）的抗總劑量輻射能力。
  5. And accomplish the simulation using csmc 0. 6m process, obtaining satisfying results

    對兩種設計方案的模擬結果進行了比較。
  6. Csmc has ccsi model which had been successfully employed in government policies and companies str - ategies in recent years

    測評中心是在中國標準化研究院與清華大學多年合作並取得豐碩科研成果的基礎上成立的。
  7. The circuit design of bandgap voltage reference is completed, considering the high order temperature compensation with real resistors. the circuits designed have been simulated, using csmc 0. 6um cmos parameter files

    在考慮利用實際電阻的溫度系數來進行帶隙基準高階溫度補償的基礎上，實現了帶隙電壓基準源的電路設計。
  8. With the development toward sub - micron and deep sub - micron technologies, cmos will have extremely wide market prospects, because its low cost and easy of implementation. hence all the simulation of this paper uses the csmc 0. 6 m standard cmos process

    標準cmos工藝作為數模混合集成電路的主流工藝，隨著cmos技術的發展，具有廣泛的市場前景，本文就是在在csmc0 . 6 m標準cmos工藝庫下進行模擬的。
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