data path 中文意思是什麼
data path
解釋
數據通道-
Mux : data path multiplexor
多重路徑數據訪問 -
Mux data path multiplexor
多重路徑數據訪問 -
2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path
我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。 -
This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor
論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。 -
In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools
本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。 -
The paper puts emphasis on research and design of coprocessor algorithm, data path, control path and modules
本文的重點是協處理器演算法、數據通道、控制通道及其模塊的設計與研究。 -
The thesis, on the basis of the diffserv model architecture, study the key realization technology of the data path and control path
本論文從diffserv模型總體結構的基礎上，研究了數據通路和控制通路的關鍵實現技術和實現結構。 -
Di ffserv model is composite of data path and control path, the data path finishes packet pretreatment and forward while the control path finishes resource manage
實現diffserv模型可以分為數據通路和控制通路兩部分，數據通路完成分組的預處理和轉發，控制通路完成資源的管理。 -
Design the data path of the risc 51 ip core. emphasis on the arithmetic logical unit ; 3. design the control path of the risc 51 ip core to make the risc 51 ip core ' s instruction set compatible with mcs51 microcontroller ; 4
（ 3 ）設計risc51ipcore控制通路，實現risc51ipcore內部指令與原mcs51指令系統的完全兼容，具體設計原mcs51指令與risc結構51核指令的轉換過程，及正確的指令時序。 -
After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages
它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。 -
After detailed analysis of microprocessor at89c51, we fixed a data path oriented scheme to test at89c51 and in this paper we have given the test program generation procedure according to most data paths of at89c51
At89c51的指令級測試以匯編測試程序作為測試激勵，實驗中通過對at89c51的詳細分析，確定了針對通路的測試策略，並給出了測試程序產生方法。 -
( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching
（ 2 ）對基於32位mips架構雙發射流水線的指令發射策略、控制相關處理和數據相關處理等流水線結構的重要問題進行深入研究，並得出了靜態發射、優化編譯指令序、第一流水線無延遲分支處理和雙流水線四通道前向數據通路等一系列能夠與32位mips架構相匹配的雙發射流 -
The experimental results indicate that it is feasible to applied at - speed current testing to at89c51 microprocessor at instruction level. through testing of data paths, we can not only detect the faults arose by data path, but also find the faults brought in by control parts
實驗結果表明，用全速電流測試在指令級對at89c51微處理器進行測試是可行的，通過測試所有的數據通路，不僅可以檢測數據通路的故障，而且可以檢測由於控制錯誤而引起的數據傳送錯誤。 -
The models are also modified to map algorithms on vliw architecture signal processors. the thesis studies the data path structure of tms320c6x and then constructs scheduling and mapping models for c6000 instructions
接著對模型進行了改進以適合信號處理演算法向超長指令字（ vliw ）的數字信號處理器進行映射，建立規劃與映射模型用於向tms320c6x進行指令映射。 -
In smp also known as " tightly coupled " multiprocessing and a " shared everything " system, processors share memory and the i o bus or data path, and a single copy of the operating system controls the processors
在smp （也稱為「緊耦合的（ tightly coupled ） 」多處理和「共享所有」的系統）中，處理器共享內存和i / o總線或者數據通路，由單一的操作系統來控制這些處理器。 -
Select and verify some algorithms of powerpc603e ' s fpu. design and implemention of the data - path of fpu, with emphasis in design a 64bit multiply - add unit. powerpc603e is a complex microporcessor system
? fpu中數據通路的設計與實現：重點是一個64bit乘加器的實現，包括部分積產生和選擇單元、 wallace壓縮單元、 161bit加法器。 -
In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io
在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。 -
Data path resumed
數據通路恢復 -
Data path suspended
數據通路掛起 -
In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed
與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。
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