decoding circuit 中文意思是什麼
decoding circuit
解釋
解碼電路-
The parallel form of the input sequence is decoded by means of a logical decoding circuit.
此并行形式序列通過邏輯解碼電路輸入。 -
There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。 -
The circuit to fulfill the byte processing function includes all parts between the modules on convolutional decoding and transfer stream de - multiplexing, consisting of the modules on data de - interleaving, rs decoding, data de - scrambling and format transforming
完成位元組處理功能的電路包括從卷積解碼輸出後到傳輸流解復用的所有部分，由解交織、 rs解碼、解擾碼和格式轉換等模塊組成。 -
In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed
其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。 -
In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld
本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。 -
Colour decoding circuit
彩色解碼電路 -
The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3. 2k internal fifo cache embedded, at the scale of 46k gates. its encoding and decoding speed are 66mhz and 47mhz respectively
布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。 -
An application of logic devices able to program to the decoding circuit
可編程邏輯器件在譯碼電路中的應用 -
The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0
本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。 -
The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit
硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。 -
On the basis of analyzing the old system and theory, the element circuits of wireless digital audio transceiver modules are designed in detail including the digital audio encoding and decoding circuits with the surrounding circuits, the fsk circuit based on pll frequency synthesizer, the power amplifier circuit, the frequency discrimination and agc circuit
在分析原系統結構和理論的基礎上，完成了整個無線數字音頻傳輸模塊各單元電路的設計。主要包括有數字音頻編碼和解碼電路及外圍電路的設計、基於鎖相頻率合成器理論的fsk電路設計、功率放大器的設計、鑒頻與agc控制電路的設計。 -
With performance of up to 900 million floating - point operations per second ( mflops ) at a clock rate of 150 mhz, tms320c6711 is fit to tackle with the problem. this thesis made a deep research on the h. 263 standard and the tms320c6711. we propose the plan of the software and the hardware for the realization of the h. 263 protocol which include the structure of the whole program, the c code of the key algorithm of the h. 263, the c code of some subprogram, and the circuit for image processing with the tms320c6711 as the processor. furthermore, we optimize some subprogram in common use to make the coding more quickly. we encode a video sequence with the tms320c6711dsk successfully, even if the compression rate is as high as 100, video effect we get after decoding the code stream is satisfying
首先系統地研究了h . 263協議編碼器的基本演算法，句法，碼流結構和tms320c6711dsk的原理結構以及ccs2 . 0的開發環境；在系統的軟體方面給出了總體流程圖，對于h . 263協議編碼器的某些核心演算法和子程序，給出了部分源代碼，對于dsp的各種代碼優化方法進行了討論，並且對代碼進行優化，從而在提高系統處理速度的同時減少代碼大小和內存需求量；硬體方面以tms320c6711為核心處理器，提出了基於tms320c6711的圖像處理平臺的硬體實現方案，並給出了原理電路圖；最後在tms320c6711dsk上成功對視頻數據進行高壓縮比（ 100倍以上）的編碼，對回傳的結果解碼后得到了令人滿意的效果。 -
The main circuit adopt boost converter topology ; the control circuit is made up of adsp - 21065l core processor, a / d converter and cpld which realize the functions of digital pulse width modulation ( dpwm ) and address decoding ; the auxiliary power supply afford work voltage of every device
。 st變換器拓撲結構；控制電路主要由核處理器adsp 、 21065l 、 al3轉換器和實現dpwm及地址解碼功能的cpld等器件組成；輔助電源電路為控制電路中各器件提供工作電壓。 -
It emphatically describes address decoding circuit and controling circuit of fpga in hardware, and describes dma transmission mode and disposing of the interrupt in driver, and describes how to get data from wav file, and how to organize data before transmition, and how to chose appropriate quantity of data transmition every time in application
著重闡述了硬體設計中fpga內部重要的譯碼及控制電路設計，驅動程序中dma （ directmemoryaccess ）的傳輸及中斷處理，應用程序中對于兩個聲音文件數據的正確獲取、組合及分割等問題。 -
Chapter two addresses in details systematic design and related modules of stand - alone door - lock system. the modules include mcu, recognition module, power, lcd, guide voice, i / o decoding circuit, rtc, unlock circuit, power save and anti - interference design
第二部分著重介紹了指紋門禁單機系統的系統總體設計以及系統中涉及到的各模塊的基礎知識、設計思路和具體實現。 -
Then, the author specially studies the characteristic of system architecture of the dsp, paints schematic principle diagram and pcb diagram of the hardware circuit system, writes the program decoding and partial data processing of the cpld, adopting verilog hdl hardware describing language
然後，研究了dsp晶元結構體系的特點，繪制了硬體電路系統的原理圖和pcb圖，且採用veriloghdl硬體描述語言編寫了復雜可編程邏輯器件（ cpld ）的譯碼與部分數據處理程序。
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