decoding logic 中文意思是什麼

decoding logic 解釋
解碼邏輯
  • decoding : 解解碼
  • logic : n. 1. 邏輯,理論學。2. 推理[方法];邏輯性,條理性。3. 威力,壓力,強制(力)。
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼; fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制;視頻數據幀存模塊為大量高速的視頻數據提供緩沖區;基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號; d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用: i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. In the process of implementation, it is essential to find a scheme to solve the following problems : ( identification of the logic channel type of signals from handsets, which is the key to determine which decoding module should be called

    本論文的主要任務是用dsp ,通過幾個模塊之間的聯調,實現基帶處理的接收模塊的功能。接收模塊主要完成gmsk解調和解碼功能,並將所解碼出的手機上行的信號傳遞給信令模塊。
  3. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  4. The communication core with a set of logic implemented the functions of coding, decoding, data buffering, message testing and command judging and performing

    數據通訊內核及其外圍邏輯完成了曼徹斯特編/解碼、數據緩沖、消息格式檢驗以及命令的解析、判斷和執行等功能。
  5. An application of logic devices able to program to the decoding circuit

    可編程邏輯器件在譯碼電路中的應用
  6. The decoding logic is shown in listing 6

    清單6顯示了解碼邏輯:
  7. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架,設計了usb的主要控制邏輯和與mcu的互連的介面(此介面與飛利普的usb介面晶元pdiusbd12兼容) ,也設計了一個數字鎖相環( dpll )來同步數據和分離時鐘,並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  8. Based on researching viterbi decoding algorithm, i design viterbi decoder on fpga using quartusii design platform of altera to design vhdl program, synthesis, simulate function logic and simulate time logic

    本設計在viterbi演算法研究基礎上對viterbi譯碼器進行fpga設計,採用altera公司的quartusii開發工具為系統開發平臺,在此平臺上進行vhdl設計、綜合、功能模擬和時序模擬。
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