delay circuit 中文意思是什麼

delay circuit 解釋
延遲電路
  • delay : vt 延遲，拖延，耽擱。 We ll delay the party for two week 我們要把會期延遲兩周。 The train was del...
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  1. By changing of the difference of write address and read address, a delayed signal from read port is achieved. the two methods have different idea but reach the same goal and have the properties that are pure digital delay, little error, compendious circuit and maneuverability

    兩種方法異曲同工，為純數字延遲，具有抗干擾性強、誤差小、電路簡明，可操作性強等優點，既體現了設計的多樣性，又體現了fpga設計的靈活可編程特性。
  2. Delay line oscillator is composed of broadband amprifer adjustable attenuator and saw sensor device. after output signal of delay line oscillator is smoothed, it mixes with 109mhz local oscillation signal. its differential frequency signal is smoothed by low - pass filter trimmed by shaping circuit and processed by digital processing circuit

    延遲線振蕩器由寬帶放大器、可調衰減器和聲表面波質量傳感器件構成。延遲線振蕩器輸出信號經濾波后與109mhz的本機晶體振蕩器輸出信號相混頻，通過低通濾波取其差頻，並經整形後由數字信號處理電路處理。
  3. A th - 1025 thoron source made in pylon company of canada was adopted. thoron gas is mixed with circulation gas before they are input into the thoron accumulation box. the thoron level in the thoron accumulation box can be adjusted by changing the gas flow rate through the thoron source, or adding different volume of delay boxes in source input circuit, and me

    簡易（氣土）室採用加拿大pylon公司生產的th - 1025型流氣式固體（氣土）源， （氣土）進入積累箱之前先與循環氣流混合，積累箱中的（氣土）濃度可以通過改變流經（氣土）源的氣流流率或在充源迴路加不同體積的延遲瓶加以調節。
  4. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  5. Abstract : a new clock - driven eco placement algorithm is presented for standard - cell layout design based on the table - lookup delay model. it considers useful clock skew information in the placement stage. it also modifies the positions of cells locally to make better preparation for the clock routing. experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently

    文摘:提出了一種新的時鐘性能驅動的增量式布局演算法，它針對目前工業界較為流行的標準單元布局，應用查找表模型來計算延遲.由於在布局階段較早地考慮到時鐘信息，可以通過調整單元位置，更有利於后續的有用偏差時鐘布線和偏差優化問題.來自於工業界的測試用例結果表明，該演算法可以有效地改善合理偏差范圍的分佈，而對電路的其它性能影響很小
  6. Reduce the load of access controller lower potential trouble nc no output, control all kinds of electric locks delay control circuit unlock delay time in 0 10s auto protection dimension : 180x77x77mm weight : 1410g

    設nc no輸出，可控制各種類型的電鎖。設延時控制電路，開鎖時間可在0 - 10秒。
  7. The main research area is the structure optimization of floating - point adder, which is intent to minimize the delay of floating - point addition and optimize the circuit structure

    主要研究方向是優化浮點加法器結構，減小浮點加法運算的延遲，優化電路結構。
  8. For high stability of the system, with the realization of hardware of the system, the second part of this paper starts from the transmission line theory, and studies the signal integrity problem of high - speed circuit system in light current. the causes of these signal integrity problems, such as signal delay, reflection, crosstalk, ground bounce noises and etc. are analyzed in theory. combined with actual design, key points of design and standard design flow of general high - speed, high - precision printed circuit board are summarized, which has been applied in actual system, and good effect has been achieved

    為使系統具有較高的穩定性，本文第二部分結合該處理器的硬體實現，從傳輸線理論出發，研究了弱電情況下高速電路印刷電路板中的信號完整性問題；從理論上分析了延遲、反射、串擾以及地彈噪聲等信號完整性問題產生的原因；結合實際設計，總結了一般高速、高精度印刷電路板的設計要點和標準設計流程，並在實際系統中獲得了應用，取得了很好的效果。
  9. The influence of the multi - layer cabling structure in integrated circuit on the signal delay

    大規模集成電路多層布線結構對信號延時的影響
  10. Interconnection dimensions become the limitation for new performance design while the size traditional transistor has met the demand of challenge. thus, the study of interconnection delay becomes more important for current circuit design and technology

    為了提高ulsi的頻率特性，按比例縮小晶體管的特徵尺寸的努力受到了互連線本徵特性和寄生效應的限制，互連線的rc延遲成為ulsi進一步提高頻率特性的瓶頸。
  11. The system parameters are developed at the same time, and some universal conclusions on the theoretical analysis of pll are reached. then, we have carried on analysis and research to the theory of differential delay ring voltage controlled oscillator ( vco ). on this basis, a improved differential delay ring vco with more efficient loads is described. this circuit has been designed and implemented in 0. 35 m cmos technology

    本文還對差分延遲結構環形壓控振蕩器電路進行了深入的分析與研究，並提出了一種基於高質量電阻電路的主從差分延遲結構環形壓控振蕩器，其採用了一種新型的主從差分延遲結構，並用一個更有效、更穩定的負載電阻電路結構來替代vco設計常使用的單個mos管電阻結構，使其系統穩定性有了相應提高。
  12. Also the emitting and receiving circuit was designed, and the emitting and receiving delay of each unit was controlled by computer

    設計了發射和接收電路，通過計算機控制實現探頭各晶片陣元的延遲發射與接收。
  13. The tripping device is basically divided into the instantaneous electromagnetic release and the time delay thermal release, which are used for protection of circuit from shortcircuit and overload respectively

    斷路器由瞬時動作的電磁脫扣器和延時動作的熱脫扣器組成，分別用作線路的短路和過載保護。
  14. Analyze item by item the position of unintact cycle, the running clearance of unintact cycle, locking - deform, datum dimension regulating, repeatly install, power voltage wave and marking running etc. at the same time, we give the calculating formula to calculating the running marking random error, and use it to calculate the system error of big diameter measure instrument - - datum dimension frame error, gyro - wheel diameter error, error caused by circumstance temperature, error caused by backing distance, angle error, delay error of data collecting circuit, lathe main shaft running error, workpiece install partial error

    對不完整圓的位置、不完整圓的轉動間隙、鎖緊變形、基準尺調整、重復安裝、電源電壓波動、標記轉動等隨機誤差進行了逐項分析，並給出轉動標記隨機誤差的計算公式。對大直徑測量儀的系統誤差?基準尺尺架誤差、滾輪直徑誤差、環境溫度引起的誤差、後退距離引起的誤差、角度誤差、數據採集電路延時誤差、車床主軸回轉誤差、工件安裝偏心誤差分別進行了計算，最後對誤差進行合成。
  15. The use of time delays on these vehicles helps to eliminate transmission and motor damage by providing even and controlled acceleration. the delay is adjustable between 0 to 5 seconds and can be wired independently of other delays or alternatively these delays can be wired in cascade so that it is necessary for the first delay to switch on before the following commences timing etc. suppression is included in the delay circuit to prevent damage by voltage transients

    延遲開關可以調整延遲時間0 ~ 5秒，並可連接數個延遲開關來逐步控制連續動作之時間（復數連接時，第一個開關要啟動接下來的開關才會跟著動作）避免電動車起動初期之電力脈沖，達到平順的起步動作，可預防電壓無端變動造成之電路故障
  16. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜指令操作均勻分配在幾個流水節拍內完成，實現了任意窗口尋址等復雜指令操作，將整個處理器的數據通路與控制通路分離，減小了電路時延，從而滿足了risc dsp不同指令功能和系統時鐘頻率的要求，構成了統一的、緊密聯系的、協調的md32系統結構。
  17. Delays ( latency ) and variability of delay ( jitter ) are greater in packet - switched than in circuit - switched networks

    更棒的是分封交換的延遲（等待時間）和延遲的變化（劇跳）是超越電路交換網路的。
  18. The circuit is based on the conventional delay - superposition algorithm realized by the field programming gate array ( fpga ). the circuit makes it possible to deinterleave and track with pri in real time

    本文還利用fpga對重頻跟蹤電路進行了設計，根據延遲重合法提出一種新的實現方案，由於不用進行首脈沖的確定，使得實時跟蹤成為可能。
  19. The pulse width trigger circuit, trigger delay circuit are discussed. and a new kind of peak detection module which is implemented by verilog hdl in fpga and greatly enhances the performance of catching glitch is discussed in the dissertation. the waveform recorder function accomplished in the scopemeter can test, monitor slow analog signals and record the characteristic value of signals continuously for a long time

    本文討論了脈寬觸發電路和觸發釋抑電路的實現，採用veriloghdl在fpga中實現了一種峰值檢測模塊，提高了示波表的毛刺捕捉能力，設計的波形記錄（ recorder ）功能模塊能夠對輸入的模擬信號進行長時間連續不斷的采樣量化，並記錄波形數據和及時送顯示。
  20. Time - delay circuit

    時間延滯電路
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