drain capacitance 中文意思是什麼

drain capacitance 解釋
漏電容
  • drain : vt 1 排去（水等液體），排泄，放干 （away; off）。2 喝乾，倒空。3 用完，花光。4 使…某物枯竭；使…耗...
  • capacitance : n. 【電學】電容；電容器。
  1. It is shown that neglecting the gate - drain capacitance of the mosfet would lead to an overestimation of the optimum device width in the cmos source degenerated lna

    本文證明了在cmos源端degeneration結構的低噪聲放大器中，忽略場效應管的柵漏電容將造成對放大管的最優柵寬估計過大。
  2. It is believed that p - si tft will be the main type in the future panel display. among the process of manufacture p - si tft, the source and drain will have the superposition with grid for the reason of machine ’ s alignment error. the superposition will bring superposition capacitance and it will badly cut down the electric performance

    在制備多晶硅tft時，由於機器的套準誤差會在柵極與源、漏極之間產生重疊部分，這樣就造成了柵源、柵漏之間的交疊電容，交疊電容的存在嚴重影響了多晶硅tft的性能，而利用自對準工藝制備的多晶硅tft則避免了交疊電容的產生。
  3. Quasi - static capacitance has been measured, when drain voltage is 0v, and gate voltage changes from ? 5v to 0v, the surface peak

    採用應力測試方法，獲得了algan / ganhemt漏極電流隨時間的變化。
  4. The lna with source inductor degeneration is analyzed in detail, which is used most widely in current. base on the analysis, a cascode structure is presented to minimize the effect of gate - drain capacitance cgd

    針對目前lna中應用最廣泛的源極電感負反饋結構，進行了詳細分析，在此基礎上對該結構做出了優化，採用共源共柵級聯結構，減小了柵漏電容cgd的影響。
  5. During the course of modeling ldmos, the paper puts forward the method in which maxwell function in the static system is applied in analysis compute of ldmos threshold voltage. schwarz - chritoffel transformation method is used to solve the gate self - capacitance with limited size. at the same time, it also provides the method which computes the drain and source self - capacitance by conformal transformation and the equivalent - voltage sharing - charge model

    在對ldmos的建模過程中，本文提出了將靜電系統中麥克斯韋方程用於ldmos閾值電壓的分析計算的方法，引入了許瓦茲-克利斯多菲變換來求解了有限尺寸的柵自電容，並提出了用保角變換和等電壓電荷共享模型來計算漏與源的自電容的方法。
  6. 2. the control signals couple through the capacitance of the switches to the output, the dynamic error caused by the parasitic gate ? drain feedthrough capacitance is significantly lowered by the use of a reduced voltage swing at the input of the switches

    2 .差分開關的控制信號會通過晶體管的寄生電容耦合到輸出，從而影響dac的動態性能，設計中通過降低控制信號電壓的方法來解決這個問題。
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