drain channel 中文意思是什麼
drain channel
解釋
排水渠-
Thus it created a conductive n channel between the source and drain.
這樣在源和漏之間就產生了一個導電的n型溝道。 -
A land drain is usually a pipe buried in farm land but it may also be an open channel.
農田的排水系統通常是埋在農田中的管子，但也可以是明渠。 -
Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet
基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高 -
The main work of this thesis analyzes the organic static induction transistor ' s operational mechanism, and researchs the change of gate length, change of gate - drain distance and change of electric channel breadth for operational characteristics influence of organic static induction transistor
本論文的主要工作是解析有機靜電感應三極體的工作機理，並研究了柵極長度變化、柵漏極間距變化和導電溝道的寬度變化對有機靜電感應三極體工作特性的影響。 -
The first important thin film from the thermal oxide group is the gate oxide layer under which a conducting channel can be formed between the souce and the drain
第一個重要的來自熱氧化組薄膜是柵氧化層，在它之下，源和漏之間就能形成導電通道。 -
Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大 -
In order to do the research works above better, we must can precisely control the width of the quasi - 1d channel and the cut off point, and also must precisely inspire current in the 2deg, so we designed the 2 channel high precision and high stability voltage source, one channel can supply the minus voltage to the split - gate, and the other one can supply the offset voltage between the source and drain pole
為了進行上述研究，必須能夠精確的控制準一維電子通道的寬度和鉗斷，以及精確的在2deg上激勵電流，由此我們設計研發了給分裂門加負偏壓和給準一維電子通道加源漏偏壓的兩路高精度高穩定性饋源。 -
The emphases of our research works are as follows : under ultra - low temperature ( about 0. 236k ) conditions, how the frequency and power of the saw and the source drain voltage influence the acoustic current ; and the relationship between the source drain current and the split - gate voltage ; and how to find the cut off voltage of the quasi - 1d electron channel ; and also the frequency character of the idt in the saw parts
研究的重點為，在甚低溫（ 0 . 236k ）下，通過實驗研究表面聲波的頻率和功率，源漏偏壓等因素對聲電電流的影響;研究準一維電子通道中不同源漏電流與分裂門負偏壓的關系，以找到分裂門的鉗斷點電壓;以及研究聲表面器件叉指換能器的頻率特性等。 -
As a result, the fermi level at the surface will shift towards the valence band maximum ( vbm ). accordingly the band bending increases, and the surface depletion layer thickness enhances, therefore, the channel thickness reduces. this is the main factor resulting in the decrease of saturated drain - source current
表面費米能級向價帶頂移動，能帶彎曲加劇，肖特基勢壘高度增加，表面耗盡層變厚，導電溝道變窄，是導致源漏飽和電流下降的主要因素。 -
In order to get strain from the channel, by process, deposit si3n4 at nmos and adopt the silicon - germanium epitaxy on source / drain by pmos, can effective improve nmos and pmos electronic characteristic
中文摘要近年來，為了提升金氧半場效電晶體工作頻率及性能，尺寸不斷微縮，讓相同面積晶片可以擁有更多的電晶體數量。 -
Construction of trapezoidal channel as a part of temporary drain at zone f
于f區建造梯形渠作為部份臨時排水系統 -
Construction of trapezoidal channel as part of the temporary drain at zone 2
於2區建造梯形渠作為部份臨時排水系統 -
Construction of trapezoidal channel as a part of temporary drain at zone b and c
于b區及c區建造梯形渠作為部份臨時排水系統 -
Ti ? the resistance measured across the channel drain and source ( or input and output ) of a bus - switch device
測量總線開關器件指定通道的源漏極間（或輸入和輸出）所得到的阻抗。 -
Under high drain voltage condition, the results proved that channel electrons are easily ejected into gan buffer layer and be trapped to induce current collapse
在大漏極電壓條件下，溝道電子易於注入到gan緩沖層中，並被緩沖層中的陷阱所俘獲，耗盡二維電子氣，從而導致電流崩塌效應。 -
We discussed the influence of channel - length modulation effect and dibl effect to temperature behavior of source - drain current, gave a expressions for studying the temperature characteristic of source - drain current, and deduced a ztc point expression
研究了溝長調制效應和漏致勢壘降低效應對漏源電流溫度特性的影響，給出了一個用於研究漏源電流溫度特性的電流公式；並推導了短溝道most的ztc點公式。 -
The source drain extension ( sde ) structure and its reliability are thoroughly studied. first, it is shown that the sde structure can suppress short channel effect effectively and the parasitic resistance at the sde region has an effect on performance. it is proposed that increasing the dose condition in the sde region can reduce the parasitic resistance and should be adopted to achieve high performance for deep submicron devices
本文對深亞微米源漏擴展mos器件結構及其可靠性進行了深入研究，首先通過模擬驗證了源漏擴展（ sde ）結構對短溝道效應的抑制， sde區寄生電阻對器件性能的影響以及sde區摻雜濃度的提高對器件性能的改善，指出了器件尺寸進一步減小后，提高源漏擴展區摻雜濃度的必要性。 -
After structure design aimed to high transconductance, parameters of device structure are modified in detail. the simulation results of soi nmos with strained si channel show great enhancements in drain current, effective mobility ( 74 % ) and transconductance ( 50 % ) beyond conventional bulk si soi nmosfet. the strained - soi nmosfet fabrication process is proposed with lt - si ( low temperature - si ) technology for relaxed sige layer and simox technology for buried oxide
其次，根據器件參量對閾值電壓和輸出特性的影響，以提高器件的跨導和電流驅動能力為目的設計了strained - soimosfet器件結構，詳細分析柵極類型和柵氧化層厚度、應變硅層厚度、 ge組分、埋氧層深度和厚度以及摻雜濃度的取值，對器件進行優化設計。 -
The effect of interface state charges on the threshold voltage, drain current, transconductance and field - effect mobility of n - channel sic mosfet is analyzed with numerical method by establishing the model of the interface state density exponential distribution
建立界面態密度的指數分佈模型，用數值方法較為詳細的分析了界面態電荷對n溝mosfet器件閾值，漏電流，跨導和場效應遷移率的影響。 -
Considering the unsymmetrical distribution of interface states induced by hot - carrier effects along the channel, the quasi - two - dimensional analysis methods are used to deduced the drain current, threshold voltage and electrical field in channel after hot - carrier degradation and the theoretical results are fully verified with the experimental data and m1ntmos6. 0 simulation output. the degradations of device output conductance, subthreshold conduction and rf characteristics are also analyzed
針對mos器件熱載流子退化所引入的界面態，根據其沿溝道非均勻分佈的模型，採用準二維分析方法對退化后器件的漏源電流、閾值電壓和飽和區溝道電場作了詳細的理論推導，並與實驗結果和器件二維數值模擬軟體minimos6 . 0的計算結果進行了驗證比較。
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