drain gate 中文意思是什麼
drain gate
解釋
泄水門-
A model of the interface state density distribution near by valence band is presented, and the dependence of the threshold voltage on temperature, the c - v characteristics and the subthreshold characteristics are predicted exactly with this model ; the effects of s / d series resistance on the output characteristics, transfer characteristics and effective mobility of sic pmosfets are analyzed. thirdly, the output characteristics and the drain breakdown characteristics are modeled with the procedure medici. the output characteristics in the room temperature and 300 ? are simulated, and the effects of gate voltage. contact resistance, interface state and other factors on sic pmos drain breakdown characteristics are analyzed
提出了一個價帶附近的界面態分佈模型，用該模型較好地描述了sicpmos器件閾值電壓隨溫度的變化關系、 c - v特性曲線以及亞閾特性曲線；分析了源漏寄生電阻對sicpmos器件輸出特性、轉移特性以及有效遷移率的影響；論文中用模擬軟體medici模擬了sicpmos器件的輸出特性和漏擊穿特性，分別模擬了室溫下和300時sicpmos器件的輸出特性，分析了柵電壓、接觸電阻、界面態以及其他因素對sicpmos擊穿特性的影響。 -
Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet
基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高 -
In gan hemt drain pulse current collapse experiments, drain current under pulse condition collapsed about 50 % than direct current condition and the pulse signal frequency affected little on current collapse. when gate voltage is small, the relationship between pulse width and drain current is i0 ( + t / 16 )
在ganhemt漏極脈沖電流崩塌測試中，發現脈沖條件下漏極電流比直流時減小大約50 % ;脈沖信號頻率對電流崩塌效應影響較小;當柵壓較小時，隨著脈沖寬度的改變漏極電流按i0 （ + t / 16 ）的規律變化。 -
It is shown that neglecting the gate - drain capacitance of the mosfet would lead to an overestimation of the optimum device width in the cmos source degenerated lna
本文證明了在cmos源端degeneration結構的低噪聲放大器中，忽略場效應管的柵漏電容將造成對放大管的最優柵寬估計過大。 -
Common - gate drain source connection
共柵漏源連接 -
Under pulse condition, charging and discharging of surface states between gate and drain induce gan hemt current collapse
脈沖條件下， ganhemt電流崩塌效應主要由柵漏之間表面態充放電引起。 -
The main work of this thesis analyzes the organic static induction transistor ' s operational mechanism, and researchs the change of gate length, change of gate - drain distance and change of electric channel breadth for operational characteristics influence of organic static induction transistor
本論文的主要工作是解析有機靜電感應三極體的工作機理，並研究了柵極長度變化、柵漏極間距變化和導電溝道的寬度變化對有機靜電感應三極體工作特性的影響。 -
In this paper, the theory of negatively charged surface states is used to investigate dynamic breakdown characteristics and the increase of gate - drain breakdown voltage as well as the reduction of saturated drain - source current after sulfur passivation. the measure which can improve the stability of sulfur passivation is proposed
本論文通過對gaasmesfet擊穿機理和硫鈍化機理的研究，用負電荷表面態理論，解釋了gaasmesfet動態擊穿特性及硫鈍化后柵漏擊穿電壓增大、源漏飽和電流減小的機理，提出了改善硫鈍化穩定性的措施。 -
In gan hemt gate pulse experiments, drain current under pulse conditon collapsed about 47 % than direct current condition and the pulse width affected little on current collapse. the relationship between drain current and pulse frequency is ncoxw [ m + ( n + k ? ) vgs + ( n + k ? ) vgs2 ] ( vgs - vth ) 2 / l
在ganhemt柵極脈沖電流崩塌測試中，觀察到柵脈沖條件下漏極電流比直流情況下減小了47 % ;隨著信號頻率的改變，漏極電流按ncoxw [ m + （ n + k -
We also studied some characteristics of sidagating effect using mesfet fabricated in planar boron implanted process including photosensitive, hysteresis, influence of sidegating effect on mesfet threshold voltage, influence of drain - source voltage on sidegating threshold voltage, influence of exchanging drain and source electrode on sidegating threshold voltage, relation between sidegating threshold voltage and the distance between side - gate and mesfet, relation between sidegating effect and floating gate, and so on
本文還採用平面選擇離子注入隔離工藝，開展了旁柵效應的光敏特性、遲滯現象、旁柵效應對mesfet閾值電壓的影響、 mesfet漏源電壓對旁柵閾值電壓的影響、漏源交換對旁柵閾值電壓的影響、旁柵閾值電壓與旁柵距的關系、旁柵效應與浮柵的關系等研究。 -
The first important thin film from the thermal oxide group is the gate oxide layer under which a conducting channel can be formed between the souce and the drain
第一個重要的來自熱氧化組薄膜是柵氧化層，在它之下，源和漏之間就能形成導電通道。 -
Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大 -
In order to do the research works above better, we must can precisely control the width of the quasi - 1d channel and the cut off point, and also must precisely inspire current in the 2deg, so we designed the 2 channel high precision and high stability voltage source, one channel can supply the minus voltage to the split - gate, and the other one can supply the offset voltage between the source and drain pole
為了進行上述研究，必須能夠精確的控制準一維電子通道的寬度和鉗斷，以及精確的在2deg上激勵電流，由此我們設計研發了給分裂門加負偏壓和給準一維電子通道加源漏偏壓的兩路高精度高穩定性饋源。 -
The emphases of our research works are as follows : under ultra - low temperature ( about 0. 236k ) conditions, how the frequency and power of the saw and the source drain voltage influence the acoustic current ; and the relationship between the source drain current and the split - gate voltage ; and how to find the cut off voltage of the quasi - 1d electron channel ; and also the frequency character of the idt in the saw parts
研究的重點為，在甚低溫（ 0 . 236k ）下，通過實驗研究表面聲波的頻率和功率，源漏偏壓等因素對聲電電流的影響;研究準一維電子通道中不同源漏電流與分裂門負偏壓的關系，以找到分裂門的鉗斷點電壓;以及研究聲表面器件叉指換能器的頻率特性等。 -
The effects of the operation temperatures, gate voltages, drain - source voltages and magnetic field upon the characteristic of device are analyzed in detail. coulomb blockade and single electron tunneling are observed in the devices. 3
詳細地分析了工作溫度、柵極電壓、漏源電壓和磁場對其特性的影響，觀測到明顯的庫侖阻塞效應和單電子隧穿效應，器件的工作溫度可達到77k以上。 -
In fet devices, the presence of an electrical field at the gate moderates the flow between the source and drain
在fet器件中，柵極電場的存在會調節源極和漏極之間的電流。 -
Quasi - static capacitance has been measured, when drain voltage is 0v, and gate voltage changes from ? 5v to 0v, the surface peak
採用應力測試方法，獲得了algan / ganhemt漏極電流隨時間的變化。 -
The result of the test for dynamic breakdown characteristics reveal that breakdown voltage increases as the lengths of the pulses applied to the gate and drain electrodes increase. this could be mainly due to the influence of surface states
Gaasmesfet動態擊穿特性測試結果表明， gaasmesfet的擊穿電壓隨柵極與漏極上所加脈沖電壓寬度的增大而增大，這主要是因為表面態的原因。 -
The lna with source inductor degeneration is analyzed in detail, which is used most widely in current. base on the analysis, a cascode structure is presented to minimize the effect of gate - drain capacitance cgd
針對目前lna中應用最廣泛的源極電感負反饋結構，進行了詳細分析，在此基礎上對該結構做出了優化，採用共源共柵級聯結構，減小了柵漏電容cgd的影響。 -
Usually series mode is used in low frequency circuit while bypass mode is used in high frequency circuit, series mode micro - switch with cantilever structure is similar to an fet, when voltage is applied on gate, and the fet will be turned on between source and drain
有靜電電壓作用在梁和底面電極時，梁發生偏轉，在源極和漏極之間實現導通，常用於自控和通信系統的信號通路空氣橋旁路開關主要用於微波段信號的通路。
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