dsp core 中文意思是什麼

dsp core 解釋
數字信號處理器內核
  • core : CORE ＝Congress of Racial Equality 〈美國〉爭取種族平等大會。n 1 果心。2 （事物、問題等的）中心，...
  1. The hardware of the ip phone codec to be designed is based on the fixed point digital signal processor ( ti ' s tms320vc5410 ) while the compression and decompression core in the software of dsp is based on the itu - t vg. 729a. ip phone codec carryout the task of collecting / playing - back. coding / decoding of speech signal and communication with embedded cpu. etc

    該語音編解碼器的硬體基於tms320vc5410 ，編解碼演算法遵循itu - tg . 729a協議，能夠實現語音信號的採集/回放、編碼/解碼以及同嵌入式cpu通信等功能，在8kbit / s的碼率下能夠提供獲得良好的語音質量。
  2. The core instrument for frequency - following is the pll. the dsp is used to realize the regulating of the dead time on - line

    用鎖相環作為頻率跟蹤的核心器件，根據最佳死區的理論，用dsp實現死區的在線調節。
  3. Chapter 4 studies scheduling algorithm of the core node to implement on single adsp2191. the result shows that a single adsp2191 chip can ’ t satisfy the bhp processing delay request and parallel processing is inevitable. chapter 5 primarily studies the core node ’ s scheduling algorithm with many dsp parallel process. details of lauc - vf scheduling algorithm analysis data flow organization and mission distribution are argued. the results of software simulation and hardware debugging indicate that many dsp parallel processing is effective and coincident with the system ’ s demand

    結果表明單片adsp2191晶元不能夠滿足核心節點對bhp的實時處理要求，必須多dsp并行處理。第五章研究了核心節點調度演算法的多dsp并行處理。對多bhp批調度演算法的實現進行分析，探討了多bhp處理任務的的劃分和分配方案;多dsp間數據通信和傳輸的dma實現;最後對多處理器并行的處理時間進行模擬測試分析。
  4. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  5. Through researching the present mainstream ip set - top box hardware system, designed an ip set - top box system which based on the adi blackfin series dsp, and chose the bf561 processor as the system core processor

    本文通過對目前主流ip機頂盒硬體系統的研究，設計了一種基於adiblackfin系列dsp的ip機頂盒方案，並選擇了blackfin系列中的雙核處理器bf561為本系統的核心處理器。
  6. Digital signal processor ( dsp ) combined with repm bldcm, which build up a dc adjustable speed system, achieve to control multiple motor speed, positive and negative rotate, protect and fault exemine by a true single chip. design and present a electromagnetism scheme of repm bldcm used in electromotion chair drive system. select electronical components and chips in the drive board by contrast with variant drive mode. design the drive board principle picture, make a drive board pcb and debug it. design a principle picture with dsp core. workout the motor control code introduced popular programme modle. test the programme reliability and control performance by linking tms320lf2407 evm, pc, drive borad and the bldcm. the bldcm swatch is prepare experiment

    本論文闡述了方波驅動稀土永磁無刷直流電動機的原理及數學模型；設計並給出了一種電動座椅用稀土永磁無刷直流電動機的電磁設計方案；對電機採用何種驅動方式進行了對比分析；對驅動電路進行了元器件選型、原理圖設計、制板及調試；有針對性的闡述了dsp在本系統應用中所涉及到的功能模塊；設計了以dsp為核心的控制電路原理圖；以模塊化的軟體編程思想編制了電機控制軟體；通過tms320lf2407目標板、上位機、驅動板及電機的聯調，證明了系統可行。
  7. High precision ad chip is used for intermediate frequency data sampling and fpga of virtex - series is used for the implementation of intermediate - frequency orthogonal system, which includes the sequencing control design for mult - channel radar system with verilog, the application of ip core of digital filter and fifo, as well as the communication control module with dsp. as the master control part, the software programming for the communication between dsp and fpga is designed. the experimental result with hardware circuit shows the design is valid and practical

    採用高精度的adc晶元完成中頻采樣，通過virtex -系列fpga設計中頻正交系統，主要包括通過verilog語言實現多路雷達中頻接收的時序控制，通過濾波器ip核實現濾波器的設計，以及利用c語言實現dsp的通訊控製程序設計。並給出了fpga在資源和速度上一些優化的方法，調試過程中影響中頻正交接收性能測試的因素。
  8. In general, the core design and research work funded by the dsp shall be conducted in hong kong unless otherwise approved

    一般而言，除非得到特別批準，否則獲設計支援計劃資助的項目，其設計和研究發展工作全部都應該在香港進行。
  9. This paper introduces a ip phone system based on dsp and arm reduced instruction set computer ( risc ) double core processor

    本文介紹的是一種基於dsp和arm精簡指令集處理器（ risc ）雙cpu處理器方案研發的ip電話系統。
  10. After that, according to the technical features of tms320 dm642 dsp, we elaborately design the program flow and data flow of the encoder. we make use of dma to transfer data to alleviate the burden of dsp core. further more we utilize many code optimization techniques to take full advantages of the parallel computation units

    之後通過分析ti公司的tms320dm642dsp的技術特點，對編碼器的程序流程和數據流進行了精心的設計，採用了dma傳輸數據以減輕dsp內核的負擔，而且採用了多種程序代碼級優化方法來充分利用dsp內核的并行計算單元，提高程序的運行速度。
  11. The dsp core of the dm642 is 32 - bit fixed - point dsps of c64x, with the performance of up to 4800 million instructions per second ( mips ) at a clock rate of 600mhz

    支持兩路ntsc / pal制式的視頻採集、處理和播放，設計了系統內部數據結構，對視頻幀圖像進行多格式軟體降采樣處理和運動檢測處理。
  12. In order to inprove the performance of md16, one method is transforming the architecture to the multi issue architecture. so a vliw dsp core is set up

    為了進一步提高md16的性能，一個可行的方式就是把單發射處理器結構轉向多發射處理器結構。
  13. The result shows that forming a high capability ac control ic using this ip as an embedded core with other cpu or dsp core can efficiently shorten the cpu processing time and constitute high performance close - loop control system. some of the ips about the communication between d / a convert, i2c devices and control ics are also created

    這種速度估算ip核作為一種通用的片內外設形式（以硬體形式完成軟體功能） ，和裸mcu （或dsp ）核製成電機控制專用晶元，可應用於各種無速度傳感器的電機控制場合。
  14. Under the two points mentioned above, we designed a 16 bits dsp core - md16

    在以上兩點的前提下，我們設計了md16的核。
  15. This dsp core is realized in a 0. 35um cmos technology and can work at above 80mhz

    最後實現在o 35微米cmos標準單元庫支持下，工作頻率可以達到80mhz以上。
  16. Next tms320c6000 dsp chip is introduced and some methods used to optimizing g. 729 according to the architecture of the dsp core is recommended

    接著介紹了tms320c6000器件以及根據其特點對itu - t提供的源代碼進行優化的一些方法。
  17. This commonly leads to a hardware dsp system partitioned into an embedded dsp core. so it is very critical to design the system and architecture of an embedded dsp core

    這將極大的提升硬體系統設計的靈活性、可靠性，以及提高硬體開發的速度和降低系統的成本。
  18. The c5471 is fairly different from common dsp chips for its dual core architecture with one arm7 core and one c54x dsp core integrated in a single chip

    Tms320vc5471是ti公司推出的一種新型結構的晶元。其最大的特點就是雙核結構：一塊arm7核和一塊tms320vc54xdsp核集成在一塊晶元內。
  19. The tester with dsp core could get excellent results by judging and adopting the different value of voltage and current, programmed amplifying and changing the frequency of sample

    系統以dsp為控制核心，可自動識別並適應不同的電壓和電流等級，採用程式控制放大、變化采樣頻率以獲得優化的陣列測試效果。
  20. The paper introduces the development of portable media player at first, then the parts of the portable media player, the designing is given based on the chip with arm and dsp core

    摘要文章首先介紹了便攜式媒體播放器的發展現狀，然後介紹了便攜式媒體播放器的組成，以及基於arm + dsp核心的便攜式媒體播放器的設計方案。
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