eda tools 中文意思是什麼

eda tools 解釋
電子設計自動化工具
  1. Covers many related topics : eda tools, vhdl, verilog ; fabrication ; fpgas, asics, microprocessors, semiconductors, cmos

    -提供it類產品資訊，評測，新聞，導購信息。擁有多商家體系的電子商務模式
  2. Covers many related topics : eda tools, vhdl, verilog ; fabrication ; fpgas, asics, microprocessors, semiconductors, cmos. usenet comp. arch -

    -提供企業級類比式與數位式kvm切換器序列操作臺控制遠端存取以及集中伺服器管理解決方案領先全球的供應廠商。
  3. Eda tools support and project support

    Eda工具的技術支持及項目支持
  4. Use cadence eda tools to design schematic, layout and make masks

    採用eda工具進行設計及出製版文件； 5
  5. The cost of eda tools also plays a role in inhibiting open hardware development and design

    Eda工具的成本也約束了開放硬體開發和設計。
  6. Openipcore then specifies the design flow for a certain project using open source eda tools

    Openipcore然後為使用開放源代碼eda工具的某個工程指定設計流程。
  7. We adopt asic design technique, using advanced eda tools to design and simulate ccu

    Ccu採用asic的全定製電路設計方法，使用先進的eda設計工具進行邏輯設計與功能模擬。
  8. We stimuli and synthesis this circuit in the eda tools software. and then give the evaluation of performance

    使用eda軟體進行模擬和綜合，根據模擬綜合的結果評價設計性能。
  9. Open source eda tools covering almost all fields of hardware design are either already available or in development

    開放資源eda工具涵蓋了幾乎全部硬體設計領域（已經可用的或正在發展中的） 。
  10. Must be a quick learner. have the ability to use eda tools and learn the methods for analog verification after short trainning

    有很強的學習能力。能夠很快學習相關的eda工具，掌握模擬驗證的方法。
  11. Use different eda tools, including modelsim, synplify, quartus, etc. at different stages of what has been designed

    在設計的不同階段使用了不同的eda工具，包括modelsim 、 synplify 、 quartus等等。
  12. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  13. In the design, we make use of two eda tools max + plus ii and protel99. because of the using of complex programmable logical device ( cpld ), we can keep untuched the original hard circuit in design and realization of counting card, so it inherited the advantage of its predecessor. in order to quantitatively analyze the performance of data acquisition system with fifo cache, we introduced the queueing theory to build mathematic model to test its quality

    在設計中藉助了max + plusii和protel99兩個eda設計軟體。由於採用了復雜可編程邏輯器件cpld ，使得在計數卡的設計和實現中不用更改原硬體電路，對原設計的優點有很好的繼承。在驗證系統改進性能時，引入排隊論建立了數學模型對系統的工作性能進行定量分析，證明其達到了設計要求。
  14. This paper introduces the general design method of soc ( system on a chip ) using eda tools, gives some cases of ip, then implement a real system on epm7128slc84 - 15, a chip of altera company, this system including : scan and recognition of matrix keyboard, calculation of add, sutu multiply under the control of state machine, the display of result on computer screen

    本文首先介紹了用eda工具設計片上系統的一般方法，給出了幾個ip ，然後在altera公司的晶元epm7128slc84 - 15上實現了一個soc實例，該實例包括：對矩陣式鍵盤的掃描、識別，在狀態機控制下進行加、減、乘法運算，以及結果在計算機屏幕的顯示。
  15. We use different commercial eda tools in order to achieve better implementation in different design phase, which include silicon ensemble of cadence, design compiler and design primer of synopsys and so on

    在設計的不同階段使用了不同的主流eda工具進行輔助設計和驗證，包括synopsys公司的邏輯綜合工具designcompiler 、靜態時序分析工具designprimer和cadence公司的自動布局布線工具siliconensemble等。
  16. In the design, we make use of the two powerful eda tools of max + plus ii and protel1 99. using max + plus ii to intergrate the ttl circuits of all the circuits make the routing of the whole board very smooth. based on the above, the auto - routing design and the imitating - test improve the quality of routing and decrease the errors of hand - routing by protel1 99, which makes a good design

    系統設計中還藉助max + plusii和protel99兩個強大的eda設計工具，採用max + plusii對整個電路中的ttl電路進行了集成化設計，使整個電路板的布線顯得流暢，在此基礎上採用protel99進行的自動布線設計以及模擬測試提高了布線的質量，減少了手動布線造成的錯誤，使得整個設計圓滿完成。
  17. This paper presents the physical implementation process of the digital asic for the wireless endoscope by eda tools

    文中給出了利用後端設計的eda工具對無線內窺鏡系統膠囊內數字集成電路進行物理實現的過程。
  18. Through the analysis of petri net models and the experimental data gained from eda tools, it is proved that the mix - execution of scalar and vector instructions " architecture is suitable for embedded microprocessor

    通過petri網模型分析與eda工具的實驗數據，證實標量向量混合執行模型適用於嵌入式微處理器的體系結構設計。
  19. Abstract : a noise model for the analog correlator used in the ultra wideband receivers is proposed due to lack of simulation capability on noise performance of the correlator in current eda tools. the analog correlator circuit is divided into several parts to calculate the equivalent noise sources respectively. the ideal impulse generators, instead of the noise sources, are then applied to obtain the time varying transfer functions. fourier transforms are carried out to explore the relationship between the noise input and output in frequency domain for each part. then the symmetrical noise sources are grouped together and the periodicity of the circuit is utilized to further simplify the model. this model can be used to evaluate noise performance of the correlator

    文摘:給出了分析模擬相關器的噪聲模型.將相關器分成不同的幾個子模塊后，對各模塊分別計算等效噪聲源.然後用理想脈沖源代替噪聲源計算電路的時變傳輸函數，接著用傅里葉變換計算輸入輸出的頻域關系.利用電路的對稱結構合併對稱的子模塊可以進一步簡化模型.該模型可以用來估計相關器的噪聲性能
  20. At last, eda tools generate netlist for semiconductor manufactory. the eda technology and veriolog hdl must speed up the design of risc cpu in china

    高性能精簡指令集微處理器的設計通過運用veriloghdl語言， eda工具，和asic設計的主要流程，縮短了設計周期，加快其產品的面市速度。
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