edge triggered flip flop 中文意思是什麼

edge triggered flip flop 解釋
邊沿觸發雙穩態電路
  • edge : n 1 刀口，（刀）刃；鋒；端；銳利。2 邊，棱，邊緣，邊界，界線，界限。3 優勢，優越條件。4 （聲調、...
  • triggered : 觸發的
  • flip : vi （ pp ）1 用指頭彈；輕輕打。2 （用鞭子等）抽。3 叭嗒叭嗒地動；翻動紙張。4 跳上車。5 起強烈反應...
  • flop : vi （ pp ）1 鼓翼；撲拍，跳動。2 啪嗒躺下[放下、坐下]；〈美俚〉上床。3 突然轉變。4 徹底失敗。vt ...
  1. From the concept of triditional master - slave flip - flop, we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input

    並且從傳統主從結構觸發器出發，提出了簡化結構的維持阻塞型觸發器設計。針對數字電路中大量存在的冗餘現象，本文討論了冗餘抑制原理以及相應的冗餘抑制技術。
  2. Detail specification for electronic component. semiconductor integrated circuit. type ch2005 dual j - k negative - edge triggered flip - flop

    電子元器件詳細規范.半導體集成電路ch2005型雙下降沿j - k觸發器
  3. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  4. Design of double - edge - triggered dynamic flip - flop and its application

    雙邊沿動態觸發器的設計及其應用
  5. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上，把利用時鐘信號競爭冒險的思想應用於三值電路中，提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
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