floating point system 中文意思是什麼

floating point system 解釋
浮點計數制
  • floating : adj. 1. 漂浮的，浮動的，流動性的。2. 【醫學】游離的。3. 移動的；不定的。4. （塗工的）第二道（漆等）。5. （船貨）未到埠的，在海上的，在運輸中的。
  • point : n 1 尖頭，尖端；尖頭器具；〈美國〉筆尖；接種針，雕刻針，編織針；小岬，小地角；【拳擊】下巴。2 【...
  • system : n 1 體系，系統；分類法；組織；設備，裝置。2 方式；方法；作業方法。3 制度；主義。4 次序，規律。5 ...
  1. 2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path

    我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。
  2. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  3. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。
  4. This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor

    論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。
  5. Based on the demonstration in the project target and the technologic support, the hilss is completely constructed, which is a tightly coupled multi - processor system composed of a standard personal computer, a high - performance single chip microprocessor system and a fast - running floating point dsp system. the debugging of the outside ecu will become easier by the friendly graphical user interface, and the high - speed signal transfer through all the parts. besides, the hilss can be expanded conveniently for its modular components

    在這一系統中， pc上位機、單片機和dsp系統通過共享存儲器構成了一個緊密耦合的多處理器平臺，友好的圖形化用戶界面、高速的信息採集和控制響應、模塊化的系統功能構成為外部電控系統的調試創造了良好的開發環境，同時也為系統今後進一步的擴展奠定了扎實便利的基礎。
  6. In the constructing of the diagnosis module using the technology of the combination of the fuzzy logic and neural network, which based on the fuzzy adaptive learning control network, a simple kind of capable method for consummate the structure and performance of network is introduced, which includes the rules extraction based on the maximum weights matrix and the parameters amendment based on genetic algorithm by floating - point coding. during the monitoring of the parts condition, the output of the condition monitoring system shows the good working condition of the executing agency by fuzzily deducing from the control instruction send by the auv ' s controller and motion status, and so offers the proof to complete mission and return safely

    在珍斷模塊建模中採用模糊邏輯與神經網路結合的技術，以模糊自適應學習控制網路為核心，提出了一種簡單可行的基於最大權值矩陣的規則提取及基於浮點數編碼的遺傳演算法的參數調整的，完善網路結構與性能的方法，並在狀態監測過程中，通過對由控制器輸入的水下機器人運動控制量以及運行狀態的模糊推理，得到執行部件（推進器或舵）的工作狀態優劣程度，為保證水下機器人完成任務，安全返回提供控制依據。
  7. Coprocessor is a crucial part of high - speed and high - precision, whose performance directly affects the capabilities of system floating - point execution

    協處理器作為高速度和高精度的關鍵運算部件，其性能直接影響系統的浮點運算能力。
  8. In a floating ? point representation system, to make an adjustment to the fixed ? point part and the corresponding adjustment to the exponent in a floating ? point representation to ensure that the fixed ? point part lies within some prescribed range, the real number represented remaining unchanged

    在浮點表示方法中，調整浮點表示中的定點部分和相應的指數，以保證定點部分處于預先規定的值域內，並使所代表的實數值保持不變。
  9. The floating - point a / d conversion scheme was employed to increase the system ' s dynamic range. complex programmable logic device ( cpld ) was also used to perform the system ' s function such as data sampling trigger control and data storage control, etc. aduc812, a new type of microprocessor with full a / d converter, was utilized to fulfill the a / d conversion

    在數據採集電路設計中，採用了浮點放大技術來提高系統的動態范圍；通過引入可編程邏輯器件來實現觸發控制、存儲控制；采樣過程中應用了時序重疊技術，從而實現了數據採集系統的流水線作業方式。
  10. Consisted of adsp21060 - sharc parallel 32 - bit floating point dsp, distributed parallel system and shared bus parallel system will satisfy signal processing tasks in sar application fields. this paper discusses range - doppler ( rd ) algorithm and two - dimension detachable algorithm in the side - looking model in synthetic aperture radar ( sar ) respectively, then studies the realization on multi - chips adsp21060 sharc dsp system

    以美國ad公司的adsp21060 - sharc （超級哈佛結構計算機）系列并行32位浮點dsp構成的分散式并行系統和共享總線式并行系統，可以滿足綜合孔徑雷達（ sar ）應用領域的信號處理任務。
  11. The ip cores used in this system include an integer processor core compatible with the intelx86 integer instruction set and an floating - point processor core compatible with the intelx86 floating - point instruction set, which are developed by ourselves

    該系統中採用的ip核主要包括自主研發的兼容intelx86定點指令集的定點微處理器核和兼容intelx86浮點指令集的浮點微處理器核，還包括片上rom核、連接soc外部的介面等。
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