floating-point hardware 中文意思是什麼
floating-point hardware
解釋
浮點硬體-
In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree
特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。 -
Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method
在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。 -
3 - d graphics on mobile phones is quite similar to 3 - d graphics on pc in years past. there is no hardware acceleration, and processor speeds are quite low, and there also is the lack of floating point arithmetic unit in mobile phones
因此論文從通用的部分開始論述，然後明了移動平臺的特徵，並試圖解釋三維引擎的一般原理和設計一個具有粗適性的基於游戲的三維圖形引擎。 -
A number of challenges needed to be met to design and implement a jpeg coding in hardware rather than in software running on a microprocessor. jpeg coding normally requires many floating - point multiplication calculations
Jpeg需要進行大量的浮點乘法運算，但用硬體實現乘法運算會佔用比實現加法運算多得多的晶元資源。 -
The rs64 family leaves things like branch prediction, exceptional floating - point powers, and hardware prefetch to its power3 cousin and focuses instead on exceptional integer performance and large, sophisticated on - and off - chip caches
Rs64系列將諸如分支預測、浮點處理以及硬體預取之類的問題留給其兄弟power3晶元來解決，自己則專注于整數運算性能和大型復雜的片上、片外緩存的處理。 -
Technique. suppose there are six steps as in ieee arithmetic hardware in a floating - point addition as shown in figure 2. a vector processor does these six steps in parallel - if the i
向量處理器可以并行處理這六個步驟如果第i個數組元素是在第4個步驟中被添加的，那麼向量處理器就會為第（ i + 1 ）個元素執行第3個步驟，為第（ i + 2 ）個元素執行第2個步驟，依此類推。 -
The chip area and power savings of not implementing floating - point in hardware can be critical in embedded microprocessors
在嵌入式微處理器中，硬體中省去浮點（支持）而為實現帶來的晶元面積和功率的減少是至關重要的。 -
With performance of up to 900 million floating - point operations per second ( mflops ) at a clock rate of 150 mhz, tms320c6711 is fit to tackle with the problem. this thesis made a deep research on the h. 263 standard and the tms320c6711. we propose the plan of the software and the hardware for the realization of the h. 263 protocol which include the structure of the whole program, the c code of the key algorithm of the h. 263, the c code of some subprogram, and the circuit for image processing with the tms320c6711 as the processor. furthermore, we optimize some subprogram in common use to make the coding more quickly. we encode a video sequence with the tms320c6711dsk successfully, even if the compression rate is as high as 100, video effect we get after decoding the code stream is satisfying
首先系統地研究了h . 263協議編碼器的基本演算法，句法，碼流結構和tms320c6711dsk的原理結構以及ccs2 . 0的開發環境；在系統的軟體方面給出了總體流程圖，對于h . 263協議編碼器的某些核心演算法和子程序，給出了部分源代碼，對于dsp的各種代碼優化方法進行了討論，並且對代碼進行優化，從而在提高系統處理速度的同時減少代碼大小和內存需求量；硬體方面以tms320c6711為核心處理器，提出了基於tms320c6711的圖像處理平臺的硬體實現方案，並給出了原理電路圖；最後在tms320c6711dsk上成功對視頻數據進行高壓縮比（ 100倍以上）的編碼，對回傳的結果解碼后得到了令人滿意的效果。 -
Note that embedded microprocessors are frequently implemented without direct hardware support for the powerpc floating - point instruction set, or only provide an interface to attach floating - point hardware
注意，嵌入式微處理器實現時經常不提供對浮點指令集的直接硬體支持，或者只是提供一個附加浮點硬體的介面。
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