formal verification 中文意思是什麼

formal verification 解釋
形式化驗證
  • formal : adj 1 正式的。2 禮節上的，儀式上的；鄭重其事的。3 形態的，外形的；形式上的；拘泥形式的，刻板的。4...
  • verification : n. 1. 證實，證明，確定；核驗，驗證，核對；檢驗，校驗。2. 【法律】訴狀[答辯書]結尾的舉證說明。
  1. Formal specification and verification of air - ticket reservation systems using pvs

    的飛機訂票系統的形式化描述與驗證
  2. Furthermore, three expanded gny logic rules are given during above analysis based on gny, and at the end of this paper, security protocol formal verification based on attack logics is discussed and presented, a development framework of integrating such verification model into automated analysis tools such as spearii is shown finally

    另外，本文在使用gny邏輯的分析過程中，提出三條實用的gny擴展規則，而在文章最後，對基於攻擊邏輯的安全協議驗證方法作了初步研究，提出了將該協議攻擊驗證技術融入協議自動分析工具的設計框架。
  3. Beginning with the formal definition of derivation set, this thesis finds the general laws of derivation set, proves the theorems about derivation set, proposes an approach for weak inversion and verification based on attribute mapping to trace data lineage, gives a series of arithmetic for data lineage tracing, describes the basic processes of data lineage, and then forms systematic theories and approach

    作者從定義起源集入手，找出了起源集的一般規律，證明了有關起源集的定理，提出了一種「基於屬性映射的弱逆與驗證」的起源集跟蹤方法，給出了一系列有關起源集跟蹤的演算法，並設計了數據志跟蹤的基本過程，從而形成了一套系統的數據志跟蹤理論與方法。
  4. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  5. Topics include : the nature of risk, formal accident and human error models, causes of accidents, fundamental concepts of system safety engineering, system and software hazard analysis, designing for safety, fault tolerance, safety issues in the design of human - machine interaction, verification of safety, creating a safety culture, and management of safety - critical projects

    其主題有：危險的性質，突發意外事件和人類錯誤模型，意外事件的因素，系統安全工程學的基本理論，系統和軟體的危險分析，安全和容錯設計，設計安全的人機交互，安全確認，創造安全文化和管理安全危急工程。
  6. This paper analyses patial sequential theory of formal verification, states the principle of modeling complex systems

    本文通過對形式驗證中部分順序理論的分析，闡述了通過串并行部序集描述復雜系統的原理。
  7. A widely distributed software package that supports the formal verification of distributed systems - is an example of temporal logic model checking for hardware verification

    一種支持分散式系統的正式驗證且廣泛發布的軟體包是用於硬體驗證的時態邏輯模型檢查的示例。
  8. The glossary significance finally manifests in the syntax structure by a certain form, the verb valence may carry on the formal verification in the syntax structure

    詞匯意義最終在句法結構中以一定形式體現出來，動詞的價可以在句法結構中進行形式驗證。
  9. Since the code is open to review by other developers as soon as it is released, there was never a formal verification cycle performed as is common in other forms of software development

    由於代碼一經發布后就公開給其他開發者進行審查，因此從來沒有出現過一個與其他形式的軟體開發類似的正式的驗證周期。
  10. Or meaning of the uml modeling concepts remained inadequate for such mdd - oriented activities as automatic code generation or formal verification

    （或含義）的規范，對這些作為自動代碼生成或正式確認的基於mdd的活動仍舊是不適當的。
  11. Formal verification of hybrid systems and its application on chemical process control

    邏輯控制器的形式驗證及其應用
  12. The method of model checking is a formal verification technique using the method of state - space search to verify if the behaviors of a given system ( the model ) satisfy a certain property that represented by temporal logic formulas, while the system presented as a kripke structure

    它通常採用狀態空間搜索的方法來檢測一個給定的計算模型是否滿足某個用時序邏輯公式表示的特定屬性。它是一個自動檢驗有限狀態並發系統的技術。
  13. At the end of the article, basic sequence is further explained together with detailed space phenomenon, which are served as the explanation and verification of abstract formal language

    文章最後一部分結合具體空間現象對基本模式加以說明，以此作為對抽象形式語言的解釋與驗證。
  14. Forth, depending on a limited syntax language, a research on the method and process of the semi - formal specification of the top level function is developed. this top level specification paves the way for the system verification and the covert channel analysis

    第四，藉助一種受限的句法語言，研究了對系統頂層功能進行半形式化規范的方法和過程，而頂層功能規范則為系統驗證、隱蔽通道分析等后繼工作奠定了基礎。
  15. And formal verification is one form of static verification

    其中形式驗證是靜態驗證的一種。
  16. Formal verification of hybrid systems

    混合系統的形式驗證方法
  17. A secure, atomic electronic commerce protocol and its formal verification

    原子的電子商務協議及其形式化驗證
  18. By doing so, some beneficial contributions are made toward the formal verification of high level secure operating systems

    從而對高安全級別操作系統的形式化驗證進行了一些有益的探索。
  19. The ccb chair and the originator determine whether formal verification of the change will be required, following the procedure in the verification section

    變更控制委員會主席和發起人決定是否需要對變更進行正式的驗證，具體的步驟在下面的驗證部分中描述。
  20. Model checking is one of the formal verification techniques to verify the correctness of system, and it is also one of the most successful automatic verification techniques in recent 20 years

    模型檢測是近二十幾年來最成功的自動檢驗技術之一，它是關于系統屬性驗證的演算法和方法。
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